Patents by Inventor Tonmoy Shingal

Tonmoy Shingal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Processes, circuits, devices, and systems for concurrent dual memory access in encryption and decryption
    Patent number: 8671254
    Abstract: A wireless communications device has two or more multiple port memory units operable to perform encryption/decryption shuffling and processing. Other circuits and methods of manufacture and operation are also disclosed.
    Type: Grant
    Filed: September 1, 2011
    Date of Patent: March 11, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Tonmoy Shingal, Chakravarthy Srinivasan, Shankaranarayana Karantha
  • PROCESS, CIRCUITS, DEVICES, AND SYSTEMS FOR ENCRYPTION AND DECRYPTION AND OTHER PURPOSES, AND PROCESSES OF MAKING
    Publication number: 20120030447
    Abstract: A wireless communications device (110) has a digital section (800) and a radio frequency section (840). The digital section (800) does setup and execution on a set of data in at least first and second threads concurrently in a series of overlapping iterations by dividing the set of data into at least two different subsets and concurrently reading and writing in both subsets. A state machine (1010, 1100) is shared by the setup and execution iterations. Two or more memory units (930, 940) segregate the set of data, the predetermined size of the set of data in the memories (930, 940) combined comprehending the total number of addresses occupied by the set of data utilized in operation of circuitry (910). Dirty bits (1430) are accessible at addresses corresponding to addresses in the memory. A selector circuit (1412) has a selector output selectively coupled to an address line, and to a data line.
    Type: Application
    Filed: September 1, 2011
    Publication date: February 2, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tonmoy Shingal, Chakravarthy Srinivasan, Shankaranarayana Karantha
  • Process, circuits, devices, and systems for encryption and decryption and other purposes, and process making
    Patent number: 8032762
    Abstract: A wireless communications device (110) has a digital section (800) and a radio frequency section (840). The digital section (800) does setup and execution on a set of data in at least first and second threads concurrently in a series of overlapping iterations by dividing the set of data into at least two different subsets and concurrently reading and writing in both subsets. A state machine (1010, 1100) is shared by the setup and execution iterations. Two or more memory units (930, 940) segregate the set of data, the predetermined size of the set of data in the memories (930, 940) combined comprehending the total number of addresses occupied by the set of data utilized in operation of circuitry (910). Dirty bits (1430) are accessible at addresses corresponding to addresses in the memory. A selector circuit (1412) has a selector output selectively coupled to an address line, and to a data line.
    Type: Grant
    Filed: September 2, 2009
    Date of Patent: October 4, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Tonmoy Shingal, Chakravarthy Srinivasan, Shankaranarayana Karantha
  • PROCESS, CIRCUITS, DEVICES, AND SYSTEMS FOR ENCRYPTION AND DECRYPTION AND OTHER PURPOSES, AND PROCESS MAKING
    Publication number: 20090323951
    Abstract: A wireless communications device (110) has a digital section (800) and a radio frequency section (840). The digital section (800) does setup and execution on a set of data in at least first and second threads concurrently in a series of overlapping iterations by dividing the set of data into at least two different subsets and concurrently reading and writing in both subsets. A state machine (1010, 1100) is shared by the setup and execution iterations. Two or more memory units (930, 940) segregate the set of data, the predetermined size of the set of data in the memories (930, 940) combined comprehending the total number of addresses occupied by the set of data utilized in operation of circuitry (910). Dirty bits (1430) are accessible at addresses corresponding to addresses in the memory. A selector circuit (1412) has a selector output selectively coupled to an address line, and to a data line.
    Type: Application
    Filed: September 2, 2009
    Publication date: December 31, 2009
    Applicant: Texas Instruments Incorporated
    Inventors: Tonmoy Shingal, Chakravarthy Srinivasan, Shankaranarayana Karantha
  • Processes, circuits, devices, and systems for encryption and decryption and other purposes, and processes of making
    Patent number: 7602905
    Abstract: A wireless communications device (110) has a digital section (800) and a radio frequency section (840). The digital section (800) does setup and execution on a set of data in at least first and second threads concurrently in a series of overlapping iterations by dividing the set of data into at least two different subsets and concurrently reading and writing in both subsets. A state machine (1010, 1100) is shared by the setup and execution iterations. Two or more memory units (930, 940) segregate the set of data, the predetermined size of the set of data in the memories (930, 940) combined comprehending the total number of addresses occupied by the set of data utilized in operation of circuitry (910). Dirty bits (1430) are accessible at addresses corresponding to addresses in the memory. A selector circuit (1412) has a selector output selectively coupled to an address line, and to a data line.
    Type: Grant
    Filed: September 1, 2004
    Date of Patent: October 13, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Tonmoy Shingal, Chakravarthy Srinivasan, Shankaranarayana Karantha
  • Processes, circuits, devices, and systems for encryption and decryption and other purposes, and processes of making
    Publication number: 20060056620
    Abstract: A wireless communications device (110) has a digital section (800) and a radio frequency section (840). The digital section (800) does setup and execution on a set of data in at least first and second threads concurrently in a series of overlapping iterations by dividing the set of data into at least two different subsets and concurrently reading and writing in both subsets. A state machine (1010, 1100) is shared by the setup and execution iterations. Two or more memory units (930, 940) segregate the set of data, the predetermined size of the set of data in the memories (930, 940) combined comprehending the total number of addresses occupied by the set of data utilized in operation of circuitry (910). Dirty bits (1430) are accessible at addresses corresponding to addresses in the memory. A selector circuit (1412) has a selector output selectively coupled to an address line, and to a data line.
    Type: Application
    Filed: September 1, 2004
    Publication date: March 16, 2006
    Inventors: Tonmoy Shingal, Chakravarthy Srinivasan, Shankaranarayana Karantha