Patents by Inventor Tonny Kamphuis
Tonny Kamphuis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11011446Abstract: A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, a backside and side surfaces extending between the major surface and the backside. The semiconductor device also includes at least one metal layer extending across the backside of the substrate. A peripheral part of the at least one metal layer located at the edge of the substrate between the backside and at least one of the side surfaces extends towards a plane containing the major surface. This can prevent burrs located at the peripheral part of the at least one metal layer interfering with the mounting of the backside of the substrate on the surface of a carrier.Type: GrantFiled: November 3, 2016Date of Patent: May 18, 2021Assignee: NEXPERIA B.V.Inventors: Tonny Kamphuis, Leo van Gemert, Hans van Rijckevorsel, Sascha Moeller, Hartmut Buenning, Steffen Holland, Y Kuang Huang
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Patent number: 10177111Abstract: Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.Type: GrantFiled: March 6, 2017Date of Patent: January 8, 2019Assignee: NXP B.V.Inventors: Tonny Kamphuis, Leonardus Antonius Elisabeth van Gemert, Roelf Anco Jacob Groenhuis, Caroline Catharina Maria Beelen-Hendrikx, Jetse de Witte, Franciscus Henrikus Martinus Swartjes
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Patent number: 10109564Abstract: This disclosure relates to a method of forming a wafer level chip scale semiconductor package, the method comprising: providing a carrier having a cavity formed therein; forming electrical contacts at a base portion and sidewalls portions of the cavity; placing a semiconductor die in the base of the cavity; connecting bond pads of the semiconductor die to the electrical contacts; encapsulating the semiconductor die; and removing the carrier to expose the electrical contacts, such that the electrical contacts are arranged directly on the encapsulation material.Type: GrantFiled: February 13, 2017Date of Patent: October 23, 2018Assignee: NXP B.V.Inventors: Roelf Groenhuis, Leo Van Gemert, Tonny Kamphuis, Jan Gulpen
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Patent number: 9953903Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device having enhanced heat dissipation. The method comprises providing a lead frame array, of a first thickness, with a plurality of die placement areas each die placement area with bond pad landings, the bond bad landings situated about a die placement area on one or multiple sides, the bond pad landings having upper surfaces and opposite lower surfaces, placing a heat sink assembly of a second thickness, having at least two mounting tabs of the first thickness, in each die placement area and attaching the at least two mounting tabs onto corresponding bond pad landings serving as anchor pads, die bonding a device die on the heat sink device assembly, conductively bonding device die bond pads to corresponding bond pad landings, and encapsulating the wire bonded device die, heat sink assembly and lead frame array in a molding compound.Type: GrantFiled: July 22, 2015Date of Patent: April 24, 2018Assignee: NXP B.V.Inventors: Leonardus Antonius Elisabeth van Gemert, Tonny Kamphuis, Rintje van der Meulen, Emil Casey Israel
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Publication number: 20170372988Abstract: This disclosure relates to a method of forming a wafer level chip scale semiconductor package, the method comprising: providing a carrier having a cavity formed therein; forming electrical contacts at a base portion and sidewalls portions of the cavity; placing a semiconductor die in the base of the cavity; connecting bond pads of the semiconductor die to the electrical contacts; encapsulating the semiconductor die; and removing the carrier to expose the electrical contacts, such that the electrical contacts are arranged directly on the encapsulation material.Type: ApplicationFiled: February 13, 2017Publication date: December 28, 2017Inventors: ROELF GROENHUIS, LEO VAN GEMERT, TONNY KAMPHUIS, JAN GULPEN
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Patent number: 9842776Abstract: Integrated circuit dies within a semiconductor wafer are separated using an approach that may facilitate mitigation of warpage, cracking and other undesirable aspects. As may be implemented in accordance with one or more embodiments, a semiconductor wafer is provided with a plurality of integrated circuit dies and first and second opposing surfaces, and with the second surface of the wafer being ground. A first mold compound is applied to the ground second surface, and the integrated circuit dies are separated along saw lanes while using the first mold compound to hold the dies in place. The integrated circuit dies are encapsulated with the mold compounds, by applying the second mold compound to the first surface and along sidewalls of the integrated circuit dies.Type: GrantFiled: January 13, 2016Date of Patent: December 12, 2017Assignee: NXP B.V.Inventors: John Suman Nakka, Tonny Kamphuis, Roelf Anco Jacob Groenhuis
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Patent number: 9798228Abstract: Consistent with an example embodiment, there is a semiconductor wafer substrate comprising a plurality of integrated circuits formed in arrays of rows and columns on the wafer substrate. A plurality of integrated circuits are in arrays of rows and columns on the wafer substrate; the rows and the columns have a first width. First and second saw lanes separate the integrated circuits, the first saw lanes are arranged parallel and equidistant with one another in a first direction defined by rows, and the second saw lanes are arranged parallel and equidistant with one another in a second direction defined by the columns. A plurality of process modules (PM) are on the wafer substrate, the PM modules defined in an at least one additional row/column having a second width. The at least one additional row/column is parallel to the plurality of device die in one direction.Type: GrantFiled: September 29, 2015Date of Patent: October 24, 2017Assignee: NXP B.V.Inventors: Hans Cobussen, Tonny Kamphuis, Heimo Scheucher, Laurentius de Kok
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Publication number: 20170200646Abstract: Integrated circuit dies within a semiconductor wafer are separated using an approach that may facilitate mitigation of warpage, cracking and other undesirable aspects. As may be implemented in accordance with one or more embodiments, a semiconductor wafer is provided with a plurality of integrated circuit dies and first and second opposing surfaces, and with the second surface of the wafer being ground. A first mold compound is applied to the ground second surface, and the integrated circuit dies are separated along saw lanes while using the first mold compound to hold the dies in place. The integrated circuit dies are encapsulated with the mold compounds, by applying the second mold compound to the first surface and along sidewalls of the integrated circuit dies.Type: ApplicationFiled: January 13, 2016Publication date: July 13, 2017Inventors: John Suman Nakka, Tonny Kamphuis, Roelf Anco Jacob Groenhuis
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Patent number: 9704823Abstract: Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.Type: GrantFiled: October 29, 2015Date of Patent: July 11, 2017Assignee: NXP B.V.Inventors: Tonny Kamphuis, Roelf Anco Jacob Groenhuis, Leonardus Antonius Elisabeth van Gemert, Caroline Catharina Maria Beelen-Hendrikx, Jetse de Witte, Franciscus Henrikus Martinus Swartjes
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Publication number: 20170179076Abstract: Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.Type: ApplicationFiled: March 6, 2017Publication date: June 22, 2017Inventors: Tonny Kamphuis, Leonardus Antonius Elisabeth van Gemert, Roelf Anco Jacob Groenhuis, Caroline Catharina Maria Beelen-Hendrikx, Jetse de Witte, Franciscus Henrikus Martinus Swartjes
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Publication number: 20170148697Abstract: A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, a backside and side surfaces extending between the major surface and the backside. The semiconductor device also includes at least one metal layer extending across the backside of the substrate. A peripheral part of the at least one metal layer located at the edge of the substrate between the backside and at least one of the side surfaces extends towards a plane containing the major surface. This can prevent burrs located at the peripheral part of the at least one metal layer interfering with the mounting of the backside of the substrate on the surface of a carrier.Type: ApplicationFiled: November 3, 2016Publication date: May 25, 2017Inventors: Tonny Kamphuis, Leo van Gemert, Hans van Rijckevorsel, Sascha Moeller, Hartmut Buenning, Steffen Holland, Y Kuang Huang
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Publication number: 20170103939Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device. The method comprises providing a lead frame, the lead frame having I/O terminals surrounding a die attach region, the lead frame defined onto a temporary carrier. A device die is attached onto the die-attach region. The device die is wire bonded to the I/O terminals, the I/O terminals located in a first position. In a molding compound the wire-bonded device die and lead frame are encapsulated. The temporary carrier is removed from the lead frame, underside surfaces of the device die and I/O terminals are exposed. Applying a non-conductive layer to the exposed underside surfaces of the device die and I/O terminals, thereby defines features in which conductive traces may be defined from the I/O terminals in the first position to customized I/O terminals located in a second position.Type: ApplicationFiled: October 9, 2015Publication date: April 13, 2017Inventors: Jan Gulpen, Leonardus Antonius Elisabeth van Gemert, Tonny Kamphuis
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Publication number: 20170092636Abstract: Consistent with an example embodiment, there is a semiconductor wafer substrate comprising a plurality of integrated circuits formed in arrays of rows and columns on the wafer substrate. A plurality of integrated circuits are in arrays of rows and columns on the wafer substrate; the rows and the columns have a first width. First and second saw lanes separate the integrated circuits, the first saw lanes are arranged parallel and equidistant with one another in a first direction defined by rows, and the second saw lanes are arranged parallel and equidistant with one another in a second direction defined by the columns. A plurality of process modules (PM) are on the wafer substrate, the PM modules defined in an at least one additional row/column having a second width. The at least one additional row/column is parallel to the plurality of device die in one direction.Type: ApplicationFiled: September 29, 2015Publication date: March 30, 2017Inventors: Tonny Kamphuis, Hans Cobussen, Heimo Scheucher, Laurentius de Kok
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Publication number: 20170025334Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device having enhanced heat dissipation. The method comprises providing a lead frame array, of a first thickness, with a plurality of die placement areas each die placement area with bond pad landings, the bond bad landings situated about a die placement area on one or multiple sides, the bond pad landings having upper surfaces and opposite lower surfaces, placing a heat sink assembly of a second thickness, having at least two mounting tabs of the first thickness, in each die placement area and attaching the at least two mounting tabs onto corresponding bond pad landings serving as anchor pads, die bonding a device die on the heat sink device assembly, conductively bonding device die bond pads to corresponding bond pad landings, and encapsulating the wire bonded device die, heat sink assembly and lead frame array in a molding compound.Type: ApplicationFiled: July 22, 2015Publication date: January 26, 2017Inventors: Leonardus Antonius Elisabeth van Gemert, Tonny Kamphuis, Rintje van der Meulen, Emil Casey Israel
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Patent number: 9466585Abstract: Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.Type: GrantFiled: October 29, 2015Date of Patent: October 11, 2016Assignee: NXP B.V.Inventors: Tonny Kamphuis, Leonardus Antonius Elisabeth van Gemert, Roelf Anco Jacob Groenhuis, Caroline Catharina Maria Beelen-Hendrikx, Franciscus Henrikus Martinus Swartjes, Jetse de Witte
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Publication number: 20160276176Abstract: Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.Type: ApplicationFiled: October 29, 2015Publication date: September 22, 2016Inventors: Tonny Kamphuis, Roelf Anco Jacob Groenhuis, Leonardus Antonius Elisabeth van Gemert, Caroline Catharina Maria Beelen-Hendrikx, Jetse de Witte, Franciscus Henrikus Martinus Swartjes
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Publication number: 20160276306Abstract: Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.Type: ApplicationFiled: October 29, 2015Publication date: September 22, 2016Inventors: Tonny Kamphuis, Leonardus Antonius Elisabeth van Gemert, Roelf Anco Jacob Groenhuis, Caroline Catharina Maria Beelen-Hendrikx, Franciscus Henrikus Martinus Swartjes, Jetse de Witte
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Dual interface IC card components and method for manufacturing the dual-interface IC card components
Patent number: 9424507Abstract: Dual-interface Integrated Circuit (IC) card components and methods for manufacturing the dual-interface IC card components are described. In an embodiment, a dual-interface IC card component includes a single-sided contact base structure, which includes a substrate with an electrical contact layer. On the single-sided contact base structure, one or more antenna contact leads are attached to the single-sided contact base structure to form a dual-interface contact structure, which is a component of a dual-interface IC card. Other embodiments are also described.Type: GrantFiled: April 1, 2014Date of Patent: August 23, 2016Assignee: NXP B.V.Inventors: Christian Zenz, Tonny Kamphuis, Johannes Wilhelmus van Rijckevorsel, Bodin Kasemset, David Ceccarelli, Boudewijn van Blokland, Patrick Schoengrundner -
Patent number: 9379071Abstract: Embodiments of a packaged semiconductor device with no leads are disclosed. One embodiment includes a semiconductor chip and a no leads package structure defining a boundary and having a bottom surface and includes three or more pads exposed at the bottom surface of the package structure. Each of the pads is located in a single inline row.Type: GrantFiled: April 17, 2014Date of Patent: June 28, 2016Assignee: NXP B.V.Inventors: Tonny Kamphuis, Jan Gulpen, Jan Willem Bergman
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Patent number: 9245804Abstract: Consistent with an example embodiment, there is a semiconductor device, with an active device having a front-side surface and a backside surface; the semiconductor device of an overall thickness, comprises an active device with circuitry defined on the front-side surface, the front-side surface having an area. The back-side of the active device has recesses f a partial depth of the active device thickness and a width of about the partial depth, the recesses surrounding the active device at vertical edges. There is a protective layer of a thickness on to the backside surface of the active device, the protective material having an area greater than the first area and having a stand-off distance. The vertical edges have the protective layer filling the recesses flush with the vertical edges. A stand-off distance of the protective material is a function of the semiconductor device thickness and the tangent of an angle (?) of tooling impact upon a vertical face the semiconductor device.Type: GrantFiled: August 14, 2013Date of Patent: January 26, 2016Assignee: NXP B.V.Inventors: Christian Zenz, Hartmut Buenning, Leonardus Antonius Elisabeth Van Gemert, Tonny Kamphuis, Sascha Moeller