Abstract: The provision of a semiconductor memory device for which access times in burst mode can be improved with no increase in the chip surface area and with no increase in power consumption. A latch pulse selection circuit 6 uses a control signal CA0T to output an input control signal SALF and a control signal SALS, to a first latch group within a latch circuit 7 as a latch pulse SAL0A, and to a second latch group within the latch circuit 7 as a latch pulse SAL1A, respectively. Based on a control signal YS0˜YS31 input from a column decoder circuit 11, a Y selector 12 is connected to a sense amplifier circuit 8 via Y switches connected to the corresponding digit lines. The sense amplifier circuit 8 comprises 256 sense amplifiers, and performs data evaluations of the signal YD0˜signal YD127 from the Y selector.

Abstract: The data to be saved by the ECC are grouped into lower digit data and higher digit data as outputs of a binary circuit, and by saving in the ECC circuit in the first established data input sequence, it is possible to save by the ECC in every lower and higher digit data delivered before reading out all data, so that the saving process time is shortened.

Abstract: A semiconductor memory device in accordance with this invention having multi-valued memory cell that stores a plurality of bits has a recognition apparatus judging whether an input address signal designates upper data or designates lower data among a plurality of bits, a row selecting apparatus selecting word lines corresponding with the input address signal and applying to selected word lines only word line voltages necessary for reading out upper data or lower data among a plurality levels of word line voltages corresponding with results of the recognition apparatus, a column selecting apparatus selecting bit lines in accordance with the input address signal, and an output apparatus generating output data in accordance with levels of the selected bit lines.