Patents by Inventor Tony A. Low
Tony A. Low has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240402400Abstract: Approaches to stack monolayer transition metal dichalcogenides (TMD) materials to develop near-perfect light absorbers (NPLAs) with only two atomic layers of TMD. Stacking TMDs may result in interlayer coupling with undesirable light absorbing behavior. The NPLAs of this disclosure stacks monolayer TMDs in such a way as to minimize TMD interlayer coupling, thus preserving TMD strong band nesting properties. Examples of approaches in this disclosure control the interlayer coupling by, for example, (a) twisted TMD bi-layers and (b) adding a buffer layer, e.g., a TMD/buffer layer/TMD tri-layer heterostructure. The NPLAs of this disclosure use the band nesting effect in TMDs, combined with a Salisbury screen geometry, to demonstrate NPLAs using only two or three uniform atomic layers of TMDs.Type: ApplicationFiled: June 4, 2024Publication date: December 5, 2024Inventors: Seungjun Lee, Dongjea Seo, Sang Hyun Park, Tony Low, Steven J. Koester, Rehan Younas, Christopher Hinkle
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Publication number: 20240319413Abstract: The subject matter of this specification can be embodied in, among other things, a graphene plasmon resonator that includes a planar patterned layer having a collection of electrically conductive segments, and a collection of dielectric segments, each dielectric segment defined between a corresponding pair of the electrically conductive segments, a graphene layer substantially parallel to the planar patterned layer and overlapping the collection of electrically conductive segments, and a planar dielectric layer between the planar patterned layer and the graphene layer.Type: ApplicationFiled: December 29, 2023Publication date: September 26, 2024Inventors: Sang-Hyun Oh, In-Ho Lee, Tony Low
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Publication number: 20240172565Abstract: A device which includes a free layer and a current channel. The free layer has a configurable magnetization state. The current channel includes a low-symmetry crystal with only one mirror plane. The low-symmetry material has relatively large unconventional spin Hall effect (SHE). A current through the current channel applies a spin-orbit torque that sets the magnetization state of the free layer.Type: ApplicationFiled: October 27, 2023Publication date: May 23, 2024Inventors: Jian-Ping Wang, Tony Low, Yifei Yang, Seungjun Lee
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Patent number: 11885985Abstract: The subject matter of this specification can be embodied in, among other things, a graphene plasmon resonator that includes a planar patterned layer having a collection of electrically conductive segments, and a collection of dielectric segments, each dielectric segment defined between a corresponding pair of the electrically conductive segments, a graphene layer substantially parallel to the planar patterned layer and overlapping the collection of electrically conductive segments, and a planar dielectric layer between the planar patterned layer and the graphene layer.Type: GrantFiled: June 5, 2020Date of Patent: January 30, 2024Assignee: Regents of the University of MinnesotaInventors: Sang-Hyun Oh, In-Ho Lee, Tony Low
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Publication number: 20230413692Abstract: Disclosed are energy efficient ferroelectric devices and methods for making such devices. For example, a ferroelectric device may be a ferroelectric tunneling junction device that includes a graphene layer on a substrate. A tunneling layer may be disposed on a portion of the graphene layer. The tunneling layer may be a ferroelectric material. A metal electrical contact layer may be disposed over the tunneling layer and the graphene layer. Additionally, some embodiments may have an additional monolayer disposed between the tunneling layer and graphene layer. By specific engineering of such layers, tunneling electroresistance performance may be substantially improved.Type: ApplicationFiled: June 20, 2023Publication date: December 21, 2023Inventors: Cheng GONG, Tony LOW, Jian-Ping WANG
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Patent number: 11552242Abstract: In some examples, a device includes a magnetic tunnel junction including a first Weyl semimetal layer, a second Weyl semimetal layer, and a dielectric layer positioned between the first and second Weyl semimetal layers. The magnetic tunnel junction may have a large tunnel magnetoresistance ratio, which may be greater than five hundred percent or even greater than one thousand percent.Type: GrantFiled: April 8, 2021Date of Patent: January 10, 2023Assignee: Regents of the University of MinnesotaInventors: Duarte José Pereira de Sousa, Cesar Octavio Ascencio, Jian-Ping Wang, Tony Low
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Publication number: 20220328757Abstract: In some examples, a device includes a magnetic tunnel junction including a first Weyl semimetal layer, a second Weyl semimetal layer, and a dielectric layer positioned between the first and second Weyl semimetal layers. The magnetic tunnel junction may have a large tunnel magnetoresistance ratio, which may be greater than five hundred percent or even greater than one thousand percent.Type: ApplicationFiled: April 8, 2021Publication date: October 13, 2022Inventors: Duarte José Pereira de Sousa, Cesar Octavio Ascencio, Jian-Ping Wang, Tony Low
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Publication number: 20200387044Abstract: The subject matter of this specification can be embodied in, among other things, a graphene plasmon resonator that includes a planar patterned layer having a collection of electrically conductive segments, and a collection of dielectric segments, each dielectric segment defined between a corresponding pair of the electrically conductive segments, a graphene layer substantially parallel to the planar patterned layer and overlapping the collection of electrically conductive segments, and a planar dielectric layer between the planar patterned layer and the graphene layer.Type: ApplicationFiled: June 5, 2020Publication date: December 10, 2020Inventors: Sang-Hyun Oh, In-Ho Lee, Tony Low
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Patent number: 8987740Abstract: A set of buried electrodes are embedded in a dielectric material layer, and a graphene layer having a doping of a first conductivity type are formed thereupon. A first upper electrode is formed over a center portion of each buried electrode. Second upper electrodes are formed in regions that do not overlie the buried electrodes. A bias voltage is applied to the set of buried electrodes to form a charged region including minority charge carriers over each of the buried electrodes, and to form a p-n junction around each portion of the graphene layer overlying a buried electrode. Charge carriers generated at the p-n junctions are collected by the first upper electrodes and the second upper electrodes, and are subsequently measured by a current measurement device or a voltage measurement device.Type: GrantFiled: September 16, 2013Date of Patent: March 24, 2015Assignee: International Business Machines CorporationInventors: Phaedon Avouris, Tony A. Low, Fengnian Xia
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Patent number: 8901689Abstract: A set of buried electrodes are embedded in a dielectric material layer, and a graphene layer having a doping of a first conductivity type are formed thereupon. A first upper electrode is formed over a center portion of each buried electrode. Second upper electrodes are formed in regions that do not overlie the buried electrodes. A bias voltage is applied to the set of buried electrodes to form a charged region including minority charge carriers over each of the buried electrodes, and to form a p-n junction around each portion of the graphene layer overlying a buried electrode. Charge carriers generated at the p-n junctions are collected by the first upper electrodes and the second upper electrodes, and are subsequently measured by a current measurement device or a voltage measurement device.Type: GrantFiled: May 10, 2013Date of Patent: December 2, 2014Assignee: International Business Machines CorporationInventors: Phaedon Avouris, Tony A. Low, Fengnian Xia
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Publication number: 20140335650Abstract: A set of buried electrodes are embedded in a dielectric material layer, and a graphene layer having a doping of a first conductivity type are formed thereupon. A first upper electrode is formed over a center portion of each buried electrode. Second upper electrodes are formed in regions that do not overlie the buried electrodes. A bias voltage is applied to the set of buried electrodes to form a charged region including minority charge carriers over each of the buried electrodes, and to form a p-n junction around each portion of the graphene layer overlying a buried electrode. Charge carriers generated at the p-n junctions are collected by the first upper electrodes and the second upper electrodes, and are subsequently measured by a current measurement device or a voltage measurement device.Type: ApplicationFiled: September 16, 2013Publication date: November 13, 2014Applicant: International Business Machines CorporationInventors: Phaedon Avouris, Tony A. Low, Fengnian Xia
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Publication number: 20140332757Abstract: A set of buried electrodes are embedded in a dielectric material layer, and a graphene layer having a doping of a first conductivity type are formed thereupon. A first upper electrode is formed over a center portion of each buried electrode. Second upper electrodes are formed in regions that do not overlie the buried electrodes. A bias voltage is applied to the set of buried electrodes to form a charged region including minority charge carriers over each of the buried electrodes, and to form a p-n junction around each portion of the graphene layer overlying a buried electrode. Charge carriers generated at the p-n junctions are collected by the first upper electrodes and the second upper electrodes, and are subsequently measured by a current measurement device or a voltage measurement device.Type: ApplicationFiled: May 10, 2013Publication date: November 13, 2014Applicant: International Business Machines CorporationInventors: Phaedon Avouris, Tony A. Low, Fengnian Xia
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Patent number: 8145777Abstract: A foreground protocol engine receives a request for rendering the contents of a packet in a recording of a protocol data stream, the protocol data stream comprising a plurality of packets. The foreground protocol engine identifies a state-snapshot having an associated timestamp previous to that of the requested packet. The foreground protocol engine displays the requested packet responsive to the identified state-snapshot.Type: GrantFiled: January 14, 2005Date of Patent: March 27, 2012Assignee: Citrix Systems, Inc.Inventors: Paul Ryman, Richard Croft, Tony Low
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Publication number: 20060161671Abstract: A recorder intercepts a protocol data stream comprising a plurality of packets, sent from a first device to a second device, the protocol data stream representing display data. The recorder copies at least one packet of the protocol data stream. The recorder creates a recording of the protocol data stream using the at least one copied packet. A protocol engine reads the at least one copied packet from the recording of the protocol data stream. The protocol engine uses information associated with the at least one copied packet to regenerate the display data represented by the protocol data stream.Type: ApplicationFiled: January 14, 2005Publication date: July 20, 2006Applicant: Citrix Systems, Inc.Inventors: Paul Ryman, Richard Croft, Tony Low
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Publication number: 20060161959Abstract: A foreground protocol engine receives a request for rendering the contents of a packet in a recording of a protocol data stream, the protocol data stream comprising a plurality of packets. The foreground protocol engine identifies a state-snapshot having an associated timestamp previous to that of the requested packet. The foreground protocol engine displays the requested packet responsive to the identified state-snapshot.Type: ApplicationFiled: January 14, 2005Publication date: July 20, 2006Applicant: Citrix Systems, Inc.Inventors: Paul Ryman, Richard Croft, Tony Low