Patents by Inventor Tony Chung Yiu KWOK
Tony Chung Yiu KWOK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10061542Abstract: Aspects of a memory and method for accessing the memory are disclosed. The memory includes a plurality of memory cells configured to support a read and write operation in a memory cycle in a first mode and a write only operation in the memory cycle in a second mode. The memory further includes a control circuit configured to generate a read clock for the read operation and a write clock for the write operation. The timing of the write clock is a function of the timing of the read clock in the first mode, and the timing of the memory cycle in the second mode.Type: GrantFiled: September 15, 2015Date of Patent: August 28, 2018Assignee: QUALCOMM IncorporatedInventors: Tony Chung Yiu Kwok, Nishith Nitin Desai, Changho Jung
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Patent number: 9978442Abstract: A memory is disclosed. The memory includes a memory array having a plurality of memory cells. The memory also includes an address decoder configured to assert a wordline to enable the memory cells. Additionally, the memory includes a tracking circuit configured to vary a duration of asserting the wordline as a function of which one of the memory cells is accessed. A method is also disclosed. The method includes asserting a wordline to enable the memory cells and varying a duration of asserting the wordline as a function of which one of a plurality of memory cells is accessed.Type: GrantFiled: September 7, 2016Date of Patent: May 22, 2018Assignee: QUALCOMM IncorporatedInventors: Bin Liang, Tony Chung Yiu Kwok, Rui Li, Sei Seung Yoon
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Patent number: 9978444Abstract: A memory and a method for operating the memory are presented. The memory includes a memory cell, a sense amplifier configured to sense read data from the memory cell, a write driver configured to provide write data to the memory cell, a first circuit configured to enable the sense amplifier during a time period, and a second circuit configured to enable the write driver during at least a portion of the time period. The method includes enabling a sense amplifier to sense read data from a memory cell during a time period and enabling a write driver to provide write data to the memory cell during at least a portion of the time period. Another memory and method for operating the memory are presented. The memory and method further include an address input circuit configured to receive a write address while the sense amplifier is enabled.Type: GrantFiled: March 22, 2016Date of Patent: May 22, 2018Assignee: QUALCOMM IncorporatedInventors: Tony Chung Yiu Kwok, Changho Jung
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Publication number: 20180068714Abstract: A memory is disclosed. The memory includes a memory array having a plurality of memory cells. The memory also includes an address decoder configured to assert a wordline to enable the memory cells. Additionally, the memory includes a tracking circuit configured to vary a duration of asserting the wordline as a function of which one of the memory cells is accessed. A method is also disclosed. The method includes asserting a wordline to enable the memory cells and varying a duration of asserting the wordline as a function of which one of a plurality of memory cells is accessed.Type: ApplicationFiled: September 7, 2016Publication date: March 8, 2018Inventors: Bin LIANG, Tony Chung Yiu KWOK, Rui LI, Sei Seung YOON
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Publication number: 20170278563Abstract: A memory and a method for operating the memory are presented. The memory includes a memory cell, a sense amplifier configured to sense read data from the memory cell, a write driver configured to provide write data to the memory cell, a first circuit configured to enable the sense amplifier during a time period, and a second circuit configured to enable the write driver during at least a portion of the time period. The method includes enabling a sense amplifier to sense read data from a memory cell during a time period and enabling a write driver to provide write data to the memory cell during at least a portion of the time period. Another memory and method for operating the memory are presented. The memory and method further include an address input circuit configured to receive a write address while the sense amplifier is enabled.Type: ApplicationFiled: March 22, 2016Publication date: September 28, 2017Inventors: Tony Chung Yiu KWOK, Changho JUNG
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Patent number: 9653152Abstract: In an aspect of the disclosure, an apparatus is provided. In one aspect, the apparatus is a memory controller that includes a logic circuit configured to generate a select signal for selecting between first and second ports of a memory as a function of first and second port signals. Additionally, the memory controller includes a switch configured to connect and disconnect the first and the second port signals. In another aspect of the disclosure, the apparatus is a storage apparatus that includes a memory and a memory controller. The memory controller includes a latch configured to latch a first port selection signal to produce a first port signal and latch a second port selection signal to produce a second port signal. The memory controller also includes a switch configured to connect and disconnect the first and the second port signals and a logic circuit configured to generate a select signal.Type: GrantFiled: November 15, 2016Date of Patent: May 16, 2017Assignee: QUALCOMM IncorporatedInventors: Tony Chung Yiu Kwok, Changho Jung
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Publication number: 20170075379Abstract: Aspects of a memory and method for accessing the memory are disclosed. The memory includes a plurality of memory cells configured to support a read and write operation in a memory cycle in a first mode and a write only operation in the memory cycle in a second mode. The memory further includes a control circuit configured to generate a read clock for the read operation and a write clock for the write operation. The timing of the write clock is a function of the timing of the read clock in the first mode, and the timing of the memory cycle in the second mode.Type: ApplicationFiled: September 15, 2015Publication date: March 16, 2017Inventors: Tony Chung Yiu KWOK, Nishith Nitin DESAI, Changho JUNG
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Publication number: 20160372167Abstract: A pseudo-dual-port (PDP) memory such as a PDP SRAM is provided that independently controls the bit line precharging and the sense amplifier precharging to increase memory operating speed while eliminating or reducing the discharge of crowbar current.Type: ApplicationFiled: June 19, 2015Publication date: December 22, 2016Inventors: Nishith Nitin Desai, Tony Chung Yiu Kwok, Changho Jung
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Patent number: 9520165Abstract: A pseudo-dual-port (PDP) memory such as a PDP SRAM is provided that independently controls the bit line precharging and the sense amplifier precharging to increase memory operating speed while eliminating or reducing the discharge of crowbar current.Type: GrantFiled: June 19, 2015Date of Patent: December 13, 2016Assignee: QUALCOMM IncorporatedInventors: Nishith Nitin Desai, Tony Chung Yiu Kwok, Changho Jung
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Patent number: 9324416Abstract: A memory and a method for operating the memory provided. In one aspect, the memory may be a PDP memory. The memory includes a control circuit configured to generate a first clock and a second clock in response an edge of a clock for an access cycle. A first input circuit is configured to receive an input for a first memory access based on the first clock. The first input circuit includes a latch. The second input circuit configured to receive an input for a second memory access based on the second clock. The second input circuit includes a flip-flop.Type: GrantFiled: August 20, 2014Date of Patent: April 26, 2016Assignee: QUALCOMM IncorporatedInventors: Sei Seung Yoon, Tony Chung Yiu Kwok, Changho Jung, Nishith Nitin Desai
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Publication number: 20160055903Abstract: A memory and a method for operating the memory provided. In one aspect, the memory may be a PDP memory. The memory includes a control circuit configured to generate a first clock and a second clock in response an edge of a clock for an access cycle. A first input circuit is configured to receive an input for a first memory access based on the first clock. The first input circuit includes a latch. The second input circuit configured to receive an input for a second memory access based on the second clock. The second input circuit includes a flip-flop.Type: ApplicationFiled: August 20, 2014Publication date: February 25, 2016Inventors: Sei Seung YOON, Tony Chung Yiu KWOK, Changho JUNG, Nishith Nitin DESAI
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Publication number: 20150310901Abstract: A memory and a method for operating the memory having a sleep mode are provided. The memory one or more storage elements and a bitline coupled to the one or more storage elements. A precharge circuit is configured to precharge the bitline during a precharge period and float the bitline during a sleep mode. An operating circuit coupled to the one or more storage elements, wherein at least one of the operating circuit and the one or more storage elements being configured to remain electrically coupled to a supply voltage in the sleep mode.Type: ApplicationFiled: April 24, 2014Publication date: October 29, 2015Applicant: QUALCOMM INCORPORATEDInventors: Changho Jung, Rakesh Vattikonda, Tony Chung Yiu Kwok
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Publication number: 20150294694Abstract: A CMOS apparatus includes a first transistor having a first transistor gate, a second transistor having a second transistor gate, a partial transistor having a gate and only one of a drain or a source. The CMOS apparatus further includes a gate interconnect connecting the first transistor gate to the second transistor gate through the gate of the partial transistor. The CMOS apparatus may be a bit cell. A write word enable line may include the gate interconnect, and the first and second transistors may enable write bit lines to the bit cell.Type: ApplicationFiled: April 11, 2014Publication date: October 15, 2015Applicant: QUALCOMM IncorporatedInventors: Changho JUNG, Tony Chung Yiu KWOK, Nishith Nitin DESAI