Abstract: A control circuit and method for controlling the electrical characteristics of an input/output (I/O) circuit such as an output driver to account for variations in fabrication process, supply voltage, and/or temperature (PVT) conditions includes a PVT controller having appropriate control logic to permit PVT compensation to be observed, tested, and selectively adjusted. The PVT controller permits selection between PVT sensing circuit-provided control signals and control signals stored in a hardware register for controlling drive strength. The PVT controller further provides the capability to offset the selected drive strength by a fixed amount and select whether or not the offset is applied and permits full testability and observability of the selected control signal, an offset value applied thereto, and the resulting output signal.

Abstract: A network interface circuit that screens out transient signals and provides an indication to the line side that an actual event has occurred, so that appropriate discrimination circuitry is powered up to determine the exact nature of the actual event only when actually needed. The present invention develops an AC signal that represents the events that are desired to be detected. This AC signal is timed so that it has a sustained rate (e.g., a 1 millisecond burst) that is unlike any transient that would occur on the line. Thus, unless the incoming signal meets the timing requirements of the circuit, it is disregarded as a being a transient and no action is taken to determine the exact nature of the signal. This avoids the need to invoke the discrimination circuits that have large power requirements until they are actually needed.

Abstract: Embodiments of the invention include a digital filtering apparatus and method for digitally filtering out undesirable or invalid data from data signal lines. The digital filtering apparatus includes a digital delay element having one or more outputs, a comparator operably connected to the outputs of the digital delay element, and a final stage operably connected to the output of the comparator and the outputs of the digital delay element. In operation, the digital filtering apparatus recognizes and filters out invalid data from data received by the digital delay element, and allows valid data to pass through the filter. Data is considered to be invalid data if its logical data state transition has a duration less than the clock setting of the digital filtering apparatus. The clock setting is established, e.g., by the number of active delay components (e.g., flip-flops) in the digital delay element and the corresponding number of active comparator inputs connected to the outputs of the active delay components.

Abstract: A method and apparatus implementing an enhanced protocol between an I2C master and an I2C slave. In various embodiments the invention permits greater addressability space and high priority access to the slave device. The enhanced protocol is implemented by the addition of command code data being transmitted which is recognized through an interface circuit inside the slave device. The invention provides an I2C solution for accessing high priority address space with one command byte, medium priority space with two command bytes and low priority space with three command bytes.

Abstract: A telephone line interface circuit with event detection capabilities is provided that screens out transient signals and provides an indication to the line side that an actual event has occurred; so that appropriate discrimination circuitry is powered up to determine the exact nature of the actual event only when needed. An event detector develops an AC signal that represents the events to be detected. This AC signal is timed to determine its sustained rate. The sustained rate has a timing threshold which is higher than a transient that occurs on the line. If the incoming signal does not meet the required threshold timing, it is disregarded as being transient and no action is taken. If the incoming signal meets the threshold requirement, the line interface circuit switches to the full power mode and facilitates the actual data transmission.