Patents by Inventor Tony G. Hamilton

Tony G. Hamilton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8301916
    Abstract: A method is described that involves storing active sleep mode software instructions to be executed by a low end central processing unit into an on chip cache that caches normal active mode software instructions executed by a high end central processing unit. The active sleep mode software instructions are to be executed by the low end central processing unit during an active sleep mode. The normal active mode software instructions are executed by the high end central processing unit during a normal active mode. The active sleep mode consumes less power than the normal active mode.
    Type: Grant
    Filed: June 8, 2010
    Date of Patent: October 30, 2012
    Assignee: Intel Corporation
    Inventor: Tony G. Hamilton
  • Publication number: 20100250989
    Abstract: A method is described that involves storing active sleep mode software instructions to be executed by a low end central processing unit into an on chip cache that caches normal active mode software instructions executed by a high end central processing unit. The active sleep mode software instructions are to be executed by the low end central processing unit during an active sleep mode. The normal active mode software instructions are executed by the high end central processing unit during a normal active mode. The active sleep mode consumes less power than the normal active mode.
    Type: Application
    Filed: June 8, 2010
    Publication date: September 30, 2010
    Inventor: Tony G. Hamilton
  • Patent number: 7734936
    Abstract: A method is described that involves storing active sleep mode software instructions to be executed by a low end central processing unit into an on chip cache of a high end central processing unit that caches normal active mode software instructions executed by the high end central processing unit. The active sleep mode software instructions are to be executed by the low end central processing unit during an active sleep mode. The normal active mode software instructions are executed by the high end central processing unit during a normal active mode. The active sleep mode consumes less power than the normal active mode.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: June 8, 2010
    Assignee: Intel Corporation
    Inventor: Tony G. Hamilton
  • Patent number: 7349995
    Abstract: An apparatus a first processor which receives a data transfer request and generates a service command that corresponds to a scalable logic block required to respond to the data transfer request, and a server computer that receives the service command and scales the scalable logic block in accordance with the service command.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: March 25, 2008
    Assignee: Intel Corporation
    Inventor: Tony G. Hamilton
  • Patent number: 7117379
    Abstract: An apparatus is described. The apparatus includes a computing system having a normal active mode and an active sleep mode. The active sleep mode consumes less power than the normal active mode. The computing system also has a high end system and a low end system. The low end system executes one or more tasks during the active sleep mode.
    Type: Grant
    Filed: August 14, 2002
    Date of Patent: October 3, 2006
    Assignee: Intel Corporation
    Inventor: Tony G. Hamilton
  • Patent number: 7058829
    Abstract: A method is described that involves storing active sleep mode software instructions to be executed by a low end central processing unit into an on chip cache that caches normal active mode software instructions executed by a high end central processing unit. The active sleep mode software instructions are to be executed by the low end central processing unit during an active sleep mode. The normal active mode software instructions are executed by the high end central processing unit during a normal active mode. The active sleep mode consumes less power than the normal active mode.
    Type: Grant
    Filed: August 14, 2002
    Date of Patent: June 6, 2006
    Assignee: Intel Corporation
    Inventor: Tony G. Hamilton
  • Publication number: 20040034803
    Abstract: An apparatus is described. The apparatus includes a computing system having a normal active mode and an active sleep mode. The active sleep mode consumes less power than the normal active mode. The computing system also has a high end system and a low end system. The low end system executes one or more tasks during the active sleep mode.
    Type: Application
    Filed: August 14, 2002
    Publication date: February 19, 2004
    Inventor: Tony G. Hamilton
  • Publication number: 20040034802
    Abstract: A method is described that involves storing active sleep mode software instructions to be executed by a low end central processing unit into an on chip cache that caches normal active mode software instructions executed by a high end central processing unit. The active sleep mode software instructions are to be executed by the low end central processing unit during an active sleep mode. The normal active mode software instructions are executed by the high end central processing unit during a normal active mode. The active sleep mode consumes less power than the normal active mode.
    Type: Application
    Filed: August 14, 2002
    Publication date: February 19, 2004
    Inventor: Tony G. Hamilton
  • Publication number: 20030208550
    Abstract: A system and method for allowing direct storage access to a notebook computers resources. The system predetermines an environment given to a wireless enabled notebook, determines if the notebook has been moved, determines if the environment has been classified, determines a system end user's identification and determines if data to be transferred has been buffered. In addition, this method matches system resources to data to be translated, executes the data transfer and returns the resources to an idle state.
    Type: Application
    Filed: June 28, 2001
    Publication date: November 6, 2003
    Inventors: Tony G. Hamilton, Marc TheBerge
  • Publication number: 20030188052
    Abstract: An apparatus a first processor which receives a data transfer request and generates a service command that corresponds to a scalable logic block required to respond to the data transfer request, and a server computer that receives the service command and scales the scalable logic block in accordance with the service command.
    Type: Application
    Filed: March 7, 2002
    Publication date: October 2, 2003
    Inventor: Tony G. Hamilton