Abstract: A semiconductor device having a capacitor integrated in a damascene structure. In one embodiment, the capacitor is formed entirely within a metallization layer of a damascene structure, having therein a semiconductor device component. Preferably, the capacitor is formed within a trench, having been etched in the dielectric material of the metal layer and the capacitor includes a first capacitor electrode formed within the recess in electrical contact with the device component of the metallization layer. An insulator may be formed over the first capacitor electrode, with a second capacitor electrode formed over the insulator. These elements are preferably conformally deposited within the trench, thereby forming a recess, a portion of which extends within the trench. A subsequently fabricated device component may then be placed in electrical contact with the second capacitor electrode.

Abstract: A method for electromagnetically shielding circuits which combine to form an integrated circuit device provides isolated silicon islands surrounded laterally and subjacently by conductive material. The isolated silicon islands may be covered individually or as a group by a conductive cover. The integrated circuit may include at least one silicon island including an analog circuit and at least one silicon island including a digital circuit, the analog and digital circuits electromagnetically shielded from one another. The method for forming the structure includes providing a first semiconductor substrate and hydrophilically bonding a substructure to the first semiconductor substrate. The substructure includes the isolated silicon islands surrounded by the conductive material. The substructure may be formed on a second semiconductor substrate by implanting an impurity region into an upper portion of the second semiconductor substrate.

Abstract: A semiconductor device having a capacitor integrated in a damascene structure. In one embodiment, the capacitor is formed entirely within a metallization layer of a damascene structure, having therein a semiconductor device component. Preferably, the capacitor is formed within a trench, having been etched in the dielectric material of the metal layer and the capacitor includes a first capacitor electrode formed within the recess in electrical contact with the device component of the metal layer. An insulator may be formed over the first capacitor electrode, with a second capacitor electrode formed over the insulator. These elements are preferably conformally deposited within the trench, thereby forming a recess, a portion of which extends within the trench. A subsequently fabricated device component may then be placed in electrical contact with the second capacitor electrode.

Abstract: A method for electromagnetically shielding circuits which combine to form an integrated circuit device provides isolated silicon islands surrounded laterally and subjacently by conductive material. The isolated silicon islands may be covered individually or as a group by a conductive cover. The integrated circuit may include at least one silicon island including an analog circuit and at least one silicon island including a digital circuit, the analog and digital circuits electromagnetically shielded from one another. The method for forming the structure includes providing a first semiconductor substrate and hydrophilically bonding a substructure to the first semiconductor substrate. The substructure includes the isolated silicon islands surrounded by the conductive material. The substructure may be formed on a second semiconductor substrate by implanting an impurity region into an upper portion of the second semiconductor substrate.

Abstract: A bipolar vertical PNP transistor compatible with CMOS processing and useful in a complementary BiMOS structure is characterized in that it is devoid of an epitaxial layer and employs a high-energy implanted phosphorus layer to provide N-type substrate isolation.

Abstract: A resistor fuse for use in a semiconductor device having an operating voltage. In one embodiment, the resistor fuse includes a silicon layer located over a semiconductor wafer and a metal silicide layer located over the silicon layer. The resistor fuse has a predetermined current threshold and is configured to open if a current through the resistor fuse at the operating voltage exceeds the current threshold.

Abstract: A wafer configured for in-process testing of electrical components has a plurality of dies disposed on the wafer, wherein adjacent dies are separated from one another by streets. An in-line device monitor having a first port, a second port, and a device-under-test substantially in line with one another is placed within a street, where the device-under-test is between the first and second ports and is electrically coupled to the first and second ports. With such an arrangement, streets having a width of 100 microns and less are suitable for accomodating a RF-device monitor having ground-signal or ground-signal-ground configurations. As a result, accurate GS or GSG RF-device monitors can be provided in narrow streets of wafers, thereby increasing the amount of wafer area available for circuitry.