Patents by Inventor Tony Gschier

Tony Gschier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12212649
    Abstract: A radar monolithic microwave integrated circuit (MMIC) includes a trigger encoder configured to receive a clock signal comprising a plurality of clock pulses having a fixed amplitude and a trigger signal configured to indicate trigger events. The trigger encoder is configured to encode the trigger signal into the clock signal to generate a distributed clock signal by skipping at least one clock pulse of the plurality of clock pulses to indicate a trigger event. The radar MMIC is configured to output the distributed clock signal having the at least one clock pulse skipped to indicate the trigger event. The radar MMIC is configured to receive the distributed clock signal as a received distributed clock signal. The radar MMIC further includes a radar operation controller configured to detect the trigger event based on the received distributed clock signal and initiate a radar operation based on detecting the trigger event.
    Type: Grant
    Filed: March 23, 2023
    Date of Patent: January 28, 2025
    Assignee: Infineon Technologies AG
    Inventors: George Efthivoulidis, Tony Gschier, Bernd Zimek, Peter Thurner, Thomas Santa
  • Publication number: 20240322993
    Abstract: A radar monolithic microwave integrated circuit (MMIC) includes a trigger encoder configured to receive a clock signal comprising a plurality of clock pulses having a fixed amplitude and a trigger signal configured to indicate trigger events. The trigger encoder is configured to encode the trigger signal into the clock signal to generate a distributed clock signal by skipping at least one clock pulse of the plurality of clock pulses to indicate a trigger event. The radar MMIC is configured to output the distributed clock signal having the at least one clock pulse skipped to indicate the trigger event. The radar MMIC is configured to receive the distributed clock signal as a received distributed clock signal. The radar MMIC further includes a radar operation controller configured to detect the trigger event based on the received distributed clock signal and initiate a radar operation based on detecting the trigger event.
    Type: Application
    Filed: March 23, 2023
    Publication date: September 26, 2024
    Inventors: George EFTHIVOULIDIS, Tony GSCHIER, Bernd ZIMEK, Peter THURNER, Thomas SANTA
  • Patent number: 7750708
    Abstract: A circuit arrangement for generating an IQ signal which comprises an oscillator (3) and a frequency divider (4). The oscillator (3) and the frequency divider (4) are arranged in a common current path between the supply and reference potentials (7, 5) in accordance with the proposed principle. It is possible to operate the two function blocks using a common BIAS current and additionally to save components.
    Type: Grant
    Filed: November 29, 2005
    Date of Patent: July 6, 2010
    Assignee: Austriamicrosystems AG
    Inventor: Tony Gschier
  • Publication number: 20090096494
    Abstract: A circuit arrangement for generating an IQ signal which comprises an oscillator (3) and a frequency divider (4). The oscillator (3) and the frequency divider (4) are arranged in a common current path between the supply and reference potentials (7, 5) in accordance with the proposed principle. It is possible to operate the two function blocks using a common BIAS current and additionally to save components.
    Type: Application
    Filed: November 29, 2005
    Publication date: April 16, 2009
    Applicant: austriamicrosystems AG
    Inventor: Tony Gschier
  • Publication number: 20080258942
    Abstract: Embodiments of sigma-delta multiplier, phase-locked loop with extended tuning range and methods for generating an RF signal are generally described herein. Other embodiments may be described and claimed. In some embodiments, a sigma-delta modulator generates an output bit stream based on an input word, multiply logic multiplies values of the output bit stream by a predetermined value, and an offset adder adds the multiplied values of the output bit stream to an offset value for use in generating a divided-frequency signal. The range of values of the input word may be reduced allowing the sigma-delta modulator to operate within a more central portion of its operating range.
    Type: Application
    Filed: April 23, 2007
    Publication date: October 23, 2008
    Applicant: INFINEON TECHNOLOGIES AG
    Inventor: Tony Gschier