Abstract: A network of matrix processing units (MPUs) is provided on a device, where each MPU is connected to at least one other MPU in the network, and each MPU is to perform matrix multiplication operations. Computer memory stores tensor data and a master control central processing unit (MCC) is provided on the device to receive an instruction from a host device, where the instruction includes one or more tensor operands based on the tensor data. The MCC invokes a set of operations on one or more of the MPUs based on the instruction, where the set of operations includes operations on the tensor operands. A result is generated from the set of operations, the result embodied as a tensor value.

Abstract: A method and apparatus for concatenating data words from a bitstream includes a scratch memory (802, 902) containing last words of unfinished blocks and left-aligned extra data words of finished blocks. A previous register (808, 908) holds one last word of an unfinished block. A next register (806, 906) holds a first of possibly many extra data words associated with the last word. A bit detector (810, 910), coupled to the previous register (808, 908) and the next register (806, 906), first concatenates the last word and the first extra data word and identifies selected bits for the detection of a valid code word. When no more valid code words can be found from the selected bits, and more data associated with the unfinished block exists, the first extra data word is moved to the previous register (808, 908) and a second extra data word is moved to the next register (806, 906). The first extra data word and the second extra data word are concatenated for the detection of another valid code word.

Abstract: New and improved methods and apparatus for run-length encoding video data. These techniques are especially suited to digital video applications, in which input to a video decoder is generated in order to determine run lengths and amplitudes. The implementations are suitable for widely-used image compression standards that integrate various algorithms into a compression system, such as the standards specified in the Digital Video Standard (the “Blue Book”).

Abstract: New and improved methods and apparatus for concatenating data words from a bitstream. These techniques are especially suited to digital video applications, in which input to a video decoder is generated in order to determine run lengths and amplitudes. This implementation is suitable for widely-used image compression standards that integrate various algorithms into a compression system, such as the standards specified in the Digital Video Standard (the “Blue Book”).

Abstract: A phase comparator compares phase of a clock signal and a generated comparison clock signal based upon rising edges. The output of the phase comparator may include a series of short up (U) pulses or down (D) pulses, depending whether the phase of the comparison clock is leading or lagging the clock. Up and down pulses U and D control an up/down shift register which in turn compensates phase difference by inserting or removing additional discrete delay elements in a variable delay line. Based upon delay signals generated by the variable delay line, a double frequency clock generator generates a 2.times. clock signal. The 2.times. clock signal is divided by 2 in a divider to supply the phase comparator with the generated comparison clock signal. The feedback scheme helps the digital delay lock loop of stabilize after a few clock cycles without additional external control.