Abstract: The disclosure relates to a viewing optic. In one embodiment, the disclosure relates to a viewing optic with an active display and an enabler interface. In one embodiment, the disclosure relates to a system comprising a viewing optic with an active display and an imaging device.

Abstract: The disclosure relates to a viewing optic with an integrated display system. In one embodiment, the viewing optic has an active display system that generates and projects the image into a first focal plane of the optical system. In yet another embodiment, the disclosure relates to a viewing optic with a power pack or battery pack.

Abstract: The disclosure relates to a viewing optic. In one embodiment, the disclosure relates to a viewing optic with an active display and a mounting system for an enabler device. In one embodiment, the disclosure relates to a viewing optic and an imaging enabler.

Abstract: The disclosure relates to a viewing optic with an integrated display system. In one embodiment, the viewing optic has an active display system that generates and projects the image into a first focal plane of the optical system. In yet another embodiment, the viewing optic has a system or device configured to track magnification setting.

Abstract: The disclosure relates to a viewing optic. In one embodiment, the disclosure relates to a viewing optic with an integrated display system. In one embodiment, the disclosure relates to a enabler configured to provide or activate or unlock select software to a viewing optic having an integrated display system.

Abstract: A method is described that involves storing active sleep mode software instructions to be executed by a low end central processing unit into an on chip cache of a high end central processing unit that caches normal active mode software instructions executed by the high end central processing unit. The active sleep mode software instructions are to be executed by the low end central processing unit during an active sleep mode. The normal active mode software instructions are executed by the high end central processing unit during a normal active mode. The active sleep mode consumes less power than the normal active mode.

Abstract: A method and apparatus to detect a power change in a system (e.g. computer) and to automatically adjust, in response to the power change, the performance states (e.g. supply voltages, clock frequencies and buffer strengths) of a plurality of system components (e.g. buses). The apparatus includes a detector and a controller.

Abstract: A system design may include electromagnetic sensors and/or placement of components to address problems of near-field electromagnetic interference caused by a processor within the system, and may further include measures to mitigate interference when detected.

Abstract: A shielded socket includes a conducting plate including a plurality of apertures, and an insulating layer. The insulating layer surrounds the conducting plate and lines at least one aperture. In an implementation, the conducting plate includes at least one grounding site.

Abstract: A shielded socket includes a conducting plate including a plurality of apertures, and an insulating layer. The insulating layer surrounds the conducting plate and lines at least one aperture. In an implementation, the conducting plate includes at least one grounding site.

Abstract: Included in the system are a memory module, a controller, and a voltage regulator. The memory module stores data indicating a level of voltage needed for operation. The controller obtains the data from the memory module and outputs a signal, based on the data, indicating the level of voltage needed by the memory module. The voltage regulator receives the signal from the controller, and supplies the level of voltage to the memory module in accordance with the signal.

Abstract: A shielded socket includes a conducting plate including a plurality of apertures, and an insulating layer. The insulating layer surrounds the conducting plate and lines at least one aperture. In an implementation, the conducting plate includes at least one grounding site.