Abstract: In one embodiment, a system to accelerate batch-normalized convolutional neural network (CNN) models is disclosed. The system extracts a plurality of first groups of layers from a first CNN model, each group of the first groups having a first convolutional layer and a first batch-norm layer. For each group of the plurality of first groups, the system calculates a first scale vector and a first shift vector based on the first batch-norm layer, and generates a second convolutional layer representing the corresponding group of the plurality of first groups based on the first convolutional layer and the first scale and the first shift vectors. The system generates an accelerated CNN model based on the second convolutional layer corresponding to the plurality of the first groups, such that the accelerated CNN model is utilized subsequently to classify an object perceived by an autonomous driving vehicle (ADV).

Abstract: In one embodiment, a system to accelerate batch-normalized convolutional neural network (CNN) models is disclosed. The system extracts a plurality of first groups of layers from a first CNN model, each group of the first groups having a first convolutional layer and a first batch-norm layer. For each group of the plurality of first groups, the system calculates a first scale vector and a first shift vector based on the first batch-norm layer, and generates a second convolutional layer representing the corresponding group of the plurality of first groups based on the first convolutional layer and the first scale and the first shift vectors. The system generates an accelerated CNN model based on the second convolutional layer corresponding to the plurality of the first groups, such that the accelerated CNN model is utilized subsequently to classify an object perceived by an autonomous driving vehicle (ADV).

Abstract: The performance of template matching is characterized by deriving the distribution of warp parameter estimate as a function of the ideal template, the ideal warp parameters and a given perturbation or noise model. An expression for the Probability Mass Function of the parameter estimate is provided. The optimal template size for template matching is the one that provides the best matching performance which is calculated from the minimum entropy of the parameter estimate.

Abstract: The present invention discloses a chip fabrication procedure as well as a simulation method for chip testing with performance pre-testing. The chip fabrication procedure with performance pre-testing comprising steps of: providing a chip design; determining if the chip design is correct by using a simulation environment; determining if the chip performance meets the standards by using a performance testing process; and proceeding with production of chips. The simulation method for chip testing comprises steps of: providing a simulation environment corresponding to a chip design; providing at least one set of testing commands; executing the testing commands; and calculating the time required for completing executing the testing commands. The present invention is advantageous since the time requited for product testing is reduced and so is the fabrication cost.

Abstract: An SRAM has a bit cell for storing a data bit in voltage mode at a data node, and a single bit line for respectively writing to and reading from said data node a data bit in reference current controlled mode. The SRAM has ultra low power consumption and can be used in word based SRAMs.

Abstract: The present invention discloses a chip fabrication procedure as well as a simulation method for chip testing with performance pre-testing. The chip fabrication procedure with performance pre-testing comprising steps of: providing a chip design; determining if the chip design is correct by using a simulation environment; determining if the chip performance meets the standards by using a performance testing process; and proceeding with production of chips. The simulation method for chip testing comprises steps of: providing a simulation environment corresponding to a chip design; providing at least one set of testing commands; executing the testing commands; and calculating the time required for completing executing the testing commands. The present invention is advantageous since the time requited for product testing is reduced and so is the fabrication cost.

Abstract: An SRAM has a bit cell for storing a data bit in voltage mode at a data node, and a single bit line for respectively writing to and reading from said data node a data bit in reference current controlled mode. The SRAM has ultra low power consumption and can be used in word based SRAMs.