Patents by Inventor Tony Joung
Tony Joung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9373680Abstract: Integrated circuits with MIM capacitors and methods for producing them with metal and oxide hard masks are provided. Embodiments include disposing a dielectric layer over an ILD, the ILD including a contact therethrough in a first region; forming a capacitor trench in the dielectric layer in a second region; forming a MIM hard mask by: disposing a first metal hard mask in the first region and in the capacitor trench in the second region; disposing an oxide hard mask over the first metal hard mask; and disposing a second metal hard mask over the oxide hard mask; forming a metal line trench through the MIM hard mask in the first region, including over the contact, while masking the second region; and removing portions of the MIM hard mask in the capacitor trench, wherein a remaining portion of the first metal hard mask comprises a bottom plate of an MIM capacitor.Type: GrantFiled: February 2, 2015Date of Patent: June 21, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Ki Young Lee, Tony Joung, Sanggil Bae
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Publication number: 20160172432Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a capacitor trench through a dielectric layer, and forming a base layer overlying the dielectric layer and within the capacitor trench. A base layer via gap is formed in the base layer, where the base layer via gap is positioned overlying the dielectric layer and the first contact. A base plate and a shield are formed from the base layer, where the base plate is within the capacitor trench. A capacitor insulating layer is formed overlying the base plate, the base layer, and within the base layer via gap, and a via is formed through the base layer via gap. A second contact and a top plate are simultaneously formed, where the second contact is formed in the via and the top plate is formed in the capacitor trench.Type: ApplicationFiled: April 29, 2015Publication date: June 16, 2016Inventors: Ki Young Lee, Sanggil Bae, Tony Joung
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Patent number: 9349787Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a capacitor trench through a dielectric layer, and forming a base layer overlying the dielectric layer and within the capacitor trench. A base layer via gap is formed in the base layer, where the base layer via gap is positioned overlying the dielectric layer and the first contact. A base plate and a shield are formed from the base layer, where the base plate is within the capacitor trench. A capacitor insulating layer is formed overlying the base plate, the base layer, and within the base layer via gap, and a via is formed through the base layer via gap. A second contact and a top plate are simultaneously formed, where the second contact is formed in the via and the top plate is formed in the capacitor trench.Type: GrantFiled: April 29, 2015Date of Patent: May 24, 2016Assignee: GLOBALFOUNDRIES, INC.Inventors: Ki Young Lee, Sanggil Bae, Tony Joung
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Patent number: 8809149Abstract: A serial capacitor comprised of a bottom electrode, a top electrode that is conductively coupled the bottom electrode, a middle electrode positioned between the bottom and top electrode, a lower dielectric layer positioned between the bottom and middle electrodes, and an upper dielectric layer positioned between the middle and the electrodes. A method includes forming the bottom electrode in a first layer of insulating material, forming the lower dielectric layer and the middle electrode above the bottom electrode, wherein the middle electrode is positioned in a second layer of insulating material, forming the upper dielectric layer above the middle electrode, forming an opening that exposes a portion of the bottom electrode, and forming the top electrode above the upper dielectric layer, wherein a portion of the top electrode extends through the opening and contacts the bottom electrode.Type: GrantFiled: December 12, 2012Date of Patent: August 19, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Ki Young Lee, Sanggil Bae, Tony Joung
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Patent number: 8795930Abstract: A self-polarized mask is provided including a transparent substrate, first and second layers of polarization material consecutively provided on the transparent substrate and polarized in a first and a second direction, respectively. A first region is provided that extends in the first direction and contains only the first layer and no second layer, a second region is provided that extends in the second direction and contains only the second layer and no first layer. Embodiments include exposing a photoresist to light through the mask such that light polarized in the first direction passes through the mask in the first region to expose a first-directional region of the photoresist layer used to form a first-directional semiconductor device structure, and light polarized in the second direction passes through the mask in the second region to expose a second-directional region of the photoresist layer used to form a second-directional semiconductor device structure.Type: GrantFiled: August 2, 2012Date of Patent: August 5, 2014Assignee: GlobalFoundries Inc.Inventors: Sanggil Bae, Ki Young Lee, Tony Joung
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Publication number: 20140159199Abstract: A serial capacitor comprised of a bottom electrode, a top electrode that is conductively coupled the bottom electrode, a middle electrode positioned between the bottom and top electrode, a lower dielectric layer positioned between the bottom and middle electrodes, and an upper dielectric layer positioned between the middle and the electrodes. A method includes forming the bottom electrode in a first layer of insulating material, forming the lower dielectric layer and the middle electrode above the bottom electrode, wherein the middle electrode is positioned in a second layer of insulating material, forming the upper dielectric layer above the middle electrode, forming an opening that exposes a portion of the bottom electrode, and forming the top electrode above the upper dielectric layer, wherein a portion of the top electrode extends through the opening and contacts the bottom electrode.Type: ApplicationFiled: December 12, 2012Publication date: June 12, 2014Applicant: GLOBALFOUNDRIES INC.Inventors: Ki Young Lee, Sanggil Bae, Tony Joung
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Publication number: 20140038089Abstract: A self-polarized mask is provided including a transparent substrate, first and second layers of polarization material consecutively provided on the transparent substrate and polarized in a first and a second direction, respectively. A first region is provided that extends in the first direction and contains only the first layer and no second layer, a second region is provided that extends in the second direction and contains only the second layer and no first layer. Embodiments include exposing a photoresist to light through the mask such that light polarized in the first direction passes through the mask in the first region to expose a first-directional region of the photoresist layer used to form a first-directional semiconductor device structure, and light polarized in the second direction passes through the mask in the second region to expose a second-directional region of the photoresist layer used to form a second-directional semiconductor device structure.Type: ApplicationFiled: August 2, 2012Publication date: February 6, 2014Applicant: GLOBALFOUNDRIES Inc.Inventors: Sanggil Bae, Ki Young Lee, Tony Joung
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Patent number: 8623735Abstract: Disclosed herein are various methods of forming semiconductor devices that have capacitor and via contacts. In one example, the method includes forming a first conductive structure and a bottom electrode of a capacitor in a layer of insulating material, forming a layer of conductive material above the first conductive structure and the bottom electrode and performing an etching process on the layer of conductive material to define a conductive material hard mask and a top electrode for the capacitor, wherein the conductive material hard mask is positioned above at least a portion of the first conductive structure. This illustrative method includes the further steps of forming an opening in the conductive material hard mask and forming a second conductive structure that extends through the opening in the conductive material hard mask and conductively contacts the first conductive structure.Type: GrantFiled: September 14, 2011Date of Patent: January 7, 2014Assignee: GLOBALFOUNDRIES Inc.Inventors: Ki Young Lee, Sanggil Bae, Tony Joung
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Publication number: 20130065375Abstract: Disclosed herein are various methods of forming semiconductor devices that have capacitor and via contacts. In one example, the method includes forming a first conductive structure and a bottom electrode of a capacitor in a layer of insulating material, forming a layer of conductive material above the first conductive structure and the bottom electrode and performing an etching process on the layer of conductive material to define a conductive material hard mask and a top electrode for the capacitor, wherein the conductive material hard mask is positioned above at least a portion of the first conductive structure. This illustrative method includes the further steps of forming an opening in the conductive material hard mask and forming a second conductive structure that extends through the opening in the conductive material hard mask and conductively contacts the first conductive structure.Type: ApplicationFiled: September 14, 2011Publication date: March 14, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Ki Young Lee, Sanggil Bae, Tony Joung