Abstract: A video processor for Distance Measuring Equipment in which all timing functions including fixed delays are performed by digital counters counting clock pulses from a highly stable source. Search and track operations are conducted by starting a memory counter by a reply from a responser and stopping the memory counter at a time corresponding to maximum range. On a succeeding interrogation cycle the memory counter is started prior to the time a reply at zero range would be received. In this cycle the memory counter begins count with the count it contained when stopped during the previous cycle; the memory counter counts until it reaches a number corresponding to maximum range, stops and initiates a range gate. A reply within the range gate causes the range gate to be repeated at the same time in the following interrogation cycle. A sufficient number of replies within the range gate cause tracking operation to begin. A velocity memory provides continuing tracking during temporary loss of reply signals.