Abstract: Approaches to stack monolayer transition metal dichalcogenides (TMD) materials to develop near-perfect light absorbers (NPLAs) with only two atomic layers of TMD. Stacking TMDs may result in interlayer coupling with undesirable light absorbing behavior. The NPLAs of this disclosure stacks monolayer TMDs in such a way as to minimize TMD interlayer coupling, thus preserving TMD strong band nesting properties. Examples of approaches in this disclosure control the interlayer coupling by, for example, (a) twisted TMD bi-layers and (b) adding a buffer layer, e.g., a TMD/buffer layer/TMD tri-layer heterostructure. The NPLAs of this disclosure use the band nesting effect in TMDs, combined with a Salisbury screen geometry, to demonstrate NPLAs using only two or three uniform atomic layers of TMDs.

Abstract: The subject matter of this specification can be embodied in, among other things, a graphene plasmon resonator that includes a planar patterned layer having a collection of electrically conductive segments, and a collection of dielectric segments, each dielectric segment defined between a corresponding pair of the electrically conductive segments, a graphene layer substantially parallel to the planar patterned layer and overlapping the collection of electrically conductive segments, and a planar dielectric layer between the planar patterned layer and the graphene layer.

Abstract: A device which includes a free layer and a current channel. The free layer has a configurable magnetization state. The current channel includes a low-symmetry crystal with only one mirror plane. The low-symmetry material has relatively large unconventional spin Hall effect (SHE). A current through the current channel applies a spin-orbit torque that sets the magnetization state of the free layer.

Abstract: The subject matter of this specification can be embodied in, among other things, a graphene plasmon resonator that includes a planar patterned layer having a collection of electrically conductive segments, and a collection of dielectric segments, each dielectric segment defined between a corresponding pair of the electrically conductive segments, a graphene layer substantially parallel to the planar patterned layer and overlapping the collection of electrically conductive segments, and a planar dielectric layer between the planar patterned layer and the graphene layer.

Abstract: Disclosed are energy efficient ferroelectric devices and methods for making such devices. For example, a ferroelectric device may be a ferroelectric tunneling junction device that includes a graphene layer on a substrate. A tunneling layer may be disposed on a portion of the graphene layer. The tunneling layer may be a ferroelectric material. A metal electrical contact layer may be disposed over the tunneling layer and the graphene layer. Additionally, some embodiments may have an additional monolayer disposed between the tunneling layer and graphene layer. By specific engineering of such layers, tunneling electroresistance performance may be substantially improved.

Abstract: In some examples, a device includes a magnetic tunnel junction including a first Weyl semimetal layer, a second Weyl semimetal layer, and a dielectric layer positioned between the first and second Weyl semimetal layers. The magnetic tunnel junction may have a large tunnel magnetoresistance ratio, which may be greater than five hundred percent or even greater than one thousand percent.

Abstract: In some examples, a device includes a magnetic tunnel junction including a first Weyl semimetal layer, a second Weyl semimetal layer, and a dielectric layer positioned between the first and second Weyl semimetal layers. The magnetic tunnel junction may have a large tunnel magnetoresistance ratio, which may be greater than five hundred percent or even greater than one thousand percent.

Abstract: The subject matter of this specification can be embodied in, among other things, a graphene plasmon resonator that includes a planar patterned layer having a collection of electrically conductive segments, and a collection of dielectric segments, each dielectric segment defined between a corresponding pair of the electrically conductive segments, a graphene layer substantially parallel to the planar patterned layer and overlapping the collection of electrically conductive segments, and a planar dielectric layer between the planar patterned layer and the graphene layer.

Abstract: A foreground protocol engine receives a request for rendering the contents of a packet in a recording of a protocol data stream, the protocol data stream comprising a plurality of packets. The foreground protocol engine identifies a state-snapshot having an associated timestamp previous to that of the requested packet. The foreground protocol engine displays the requested packet responsive to the identified state-snapshot.

Abstract: A recorder intercepts a protocol data stream comprising a plurality of packets, sent from a first device to a second device, the protocol data stream representing display data. The recorder copies at least one packet of the protocol data stream. The recorder creates a recording of the protocol data stream using the at least one copied packet. A protocol engine reads the at least one copied packet from the recording of the protocol data stream. The protocol engine uses information associated with the at least one copied packet to regenerate the display data represented by the protocol data stream.

Abstract: A foreground protocol engine receives a request for rendering the contents of a packet in a recording of a protocol data stream, the protocol data stream comprising a plurality of packets. The foreground protocol engine identifies a state-snapshot having an associated timestamp previous to that of the requested packet. The foreground protocol engine displays the requested packet responsive to the identified state-snapshot.

Abstract: A chip control insert is disclosed having positive, concave radiused chip breaker entry surfaces, and a locating surface which is equipped with a planar sealing surface and inclined, convex, radiused chip breaker ramp surfaces which undulate along the length of the insert. The intersection of the back ramp surface and the entry surface defines a chip groove. The locating surface has radial nose projections and radius bulges intermediate the length of the polygon sides of the insert.