Patents by Inventor Tony Mule?

Tony Mule? has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7554347
    Abstract: Optoelectronic probe cards, methods of fabrication, and methods of use, are disclosed. Briefly described, one exemplary embodiment includes an optoelectronic probe card adapted to test an electrical quality and an optical quality of an optoelectronic structure under test having electrical and optical components.
    Type: Grant
    Filed: March 17, 2003
    Date of Patent: June 30, 2009
    Assignee: Georgia Tech Research Corporation
    Inventors: Tony Mule′, Hiren Thacker, Muhannad Bakir, James D. Meindl, Thomas K. Gaylord, Kevin P. Martin, Paul Kohl
  • Publication number: 20070059913
    Abstract: An apparatus for reducing amine poisoning of photoresist layers comprises a substrate, an etch stop layer containing amines formed over the substrate, and a dense capping layer formed directly on the etch stop layer, wherein the dense capping layer substantially prevents the amines from diffusing out of the etch stop layer and into a subsequently formed photoresist layer. The dense capping layer may comprise silicon carbide, silicon carboxide, or a combination of silicon carbide and silicon carboxide. The dense capping layer may have a density greater than or equal to 2 g/cm3 and a thickness that ranges from 10 ? to 200 ?.
    Type: Application
    Filed: September 15, 2005
    Publication date: March 15, 2007
    Inventors: Sean King, George Antonelli, Tony Mule
  • Patent number: 7016569
    Abstract: Systems and methods for back-of-die, through-wafer guided-wave optical clock distribution systems (networks) are disclosed. A representative back-of-die, through-wafer guided-wave optical clock distribution system includes an integrated circuit device with a first cladding layer disposed on the back-side of the integrated circuit device, and an core layer disposed on the first cladding layer. The core layer, the first cladding layer, or the second cladding layer can include, but is not limited to, vertical-to-horizontal input diffraction gratings, a horizontal-to-horizontal diffraction gratings, and horizontal-to-vertical output diffraction gratings.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: March 21, 2006
    Assignee: Georgia Tech Research Corporation
    Inventors: Tony Mule, James D. Meindl, Thomas K. Gaylord
  • Publication number: 20050257709
    Abstract: Systems and methods for three dimensional lithography, nano-indentation, and combinations thereof are disclosed.
    Type: Application
    Filed: October 31, 2003
    Publication date: November 24, 2005
    Inventors: Tony Mule, Paul Kohl, Muhannad Bakir, Kevin Martin, James Meindl, Hiren Thacker
  • Patent number: 6954576
    Abstract: Wafer-level electronic packages having waveguides and methods of fabricating chip-level electronic packages having waveguides are disclosed. A representative chip-level electronic package includes at least one waveguide having a waveguide core. In addition, another representative chip-level electronic package includes a waveguide having an air-gap cladding layer around a portion of the waveguide core. A representative method for fabricating a chip-level electronic package includes: providing a substrate having a passivation layer disposed on the substrate; disposing a waveguide core on a portion of the passivation layer; disposing a first sacrificial layer onto at least one portion of the passivation layer and the waveguide core; disposing an overcoat layer onto the passivation layer and the first sacrificial layer; and removing the first sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and around a portion of the waveguide core.
    Type: Grant
    Filed: July 21, 2004
    Date of Patent: October 11, 2005
    Assignee: Georgia Tech Research Corporation
    Inventors: Tony Mule′, Chirag Patel, James D. Meindl, Thomas K. Gaylord, Elias N. Glytsis, Kevin P. Martin, Stephen M. Schultz, Muhannad Bakir, Hollie Reed, Paul Kohl
  • Patent number: 6947651
    Abstract: Waveguides and methods of fabrication thereof are presented. A representative waveguide includes a waveguide core and a cladding layer, where the cladding layer surrounds the waveguide core. The waveguide core and cladding can be made of a host material having a plurality of nano-pores, wherein the nano-pores include a sacrificial material, and the sacrificial material can be selectively decomposed in both the core and cladding layers to form a plurality of nano air-gaps.
    Type: Grant
    Filed: May 10, 2002
    Date of Patent: September 20, 2005
    Assignee: Georgia Tech Research Corporation
    Inventors: Tony Mule′ , Paul Kohl, James D. Meindl, Agnes Padovani, Thomas K. Gaylord, Elias N. Glytsis, Sue Ann B. Allen
  • Publication number: 20040264840
    Abstract: Wafer-level electronic packages having waveguides and methods of fabricating chip-level electronic packages having waveguides are disclosed. A representative chip-level electronic package includes at least one waveguide having a waveguide core. In addition, another representative chip-level electronic package includes a waveguide having an air-gap cladding layer around a portion of the waveguide core. A representative method for fabricating a chip-level electronic package includes: providing a substrate having a passivation layer disposed on the substrate; disposing a waveguide core on a portion of the passivation layer; disposing a first sacrificial layer onto at least one portion of the passivation layer and the waveguide core; disposing an overcoat layer onto the passivation layer and the first sacrificial layer; and removing the first sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and around a portion of the waveguide core.
    Type: Application
    Filed: July 21, 2004
    Publication date: December 30, 2004
    Inventors: Tony Mule, Chirag Patel, James D. Meindl, Thomas K. Gaylord, Elias N. Glytsis, Kevin P. Martin, Stephen M. Schultz, Muhannad Bakir, Hollie Reed, Paul Kohl
  • Patent number: 6807352
    Abstract: Waveguides having air-gap cladding layers and methods of fabricating waveguides having air-gap cladding layers are disclosed. A representative waveguide includes a waveguide core having an air-gap cladding layer engaging a portion of the waveguide core. In addition, a representative method of fabricating a waveguide having an air-gap cladding layer includes: providing a substrate having a lower cladding layer disposed on the substrate; disposing a waveguide core on a portion of the lower cladding layer; disposing a sacrificial layer onto at least one portion of the lower cladding layer and the waveguide core; disposing an overcoat layer onto the lower cladding layer and the sacrificial layer; and removing the sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and engaging a portion of the waveguide core.
    Type: Grant
    Filed: February 11, 2002
    Date of Patent: October 19, 2004
    Assignee: Georgia Tech Research Corporation
    Inventors: Tony Mule′, James D. Meindl, Thomas K. Gaylord, Elias N. Glytsis, Paul Kohl
  • Patent number: 6788867
    Abstract: Optical interconnect layers and methods of fabrication thereof are described. In addition, the optical interconnect layers integrated into devices such as backplane (BP), printed wiring board (PWB), and multi-chip module (MCM) level devices are described. A representative optical interconnect layer includes a first cladding layer, a second cladding layer, one or more waveguides having a waveguide core and an air-gap cladding layer engaging a portion of waveguide core, wherein the first cladding layer and the second cladding layer engage the waveguide.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: September 7, 2004
    Assignee: Georgia Tech Research Corp.
    Inventors: Tony Mule′, James D. Meindl, Paul Kohl, Stephen M. Schultz, Thomas K. Gaylord, Elias N. Glytsis, Ricardo Villalaz, Muhannad Bakir, Hollie Reed
  • Patent number: 6785458
    Abstract: Wafer-level electronic packages having waveguides and methods of fabricating chip-level electronic packages having waveguides are disclosed. A representative chip-level electronic package includes at least one waveguide having a waveguide core. In addition, another representative chip-level electronic package includes a waveguide having an air-gap cladding layer around a portion of the waveguide core. A representative method for fabricating a chip-level electronic package includes: providing a substrate having a passivation layer disposed on the substrate; disposing a waveguide core on a portion of the passivation layer; disposing a first sacrificial layer onto at least one portion of the passivation layer and the waveguide core; disposing an overcoat layer onto the passivation layer and the first sacrificial layer; and removing the first sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and around a portion of the waveguide core.
    Type: Grant
    Filed: February 11, 2002
    Date of Patent: August 31, 2004
    Assignee: Georgia Tech Research Corporation
    Inventors: Tony Mule′, Chirag Patel, James D. Meindl, Thomas K. Gaylord, Elias N. Glytsis, Kevin P. Martin, Stephen M. Schultz, Muhannad Bakir, Hollie Reed, Paul Kohl
  • Publication number: 20040126076
    Abstract: Optical interconnect layers and methods of fabrication thereof are described. In addition, the optical interconnect layers integrated into devices such as backplane (BP), printed wiring board (PWB), and multi-chip module (MCM) level devices are described. A representative optical interconnect layer includes a first cladding layer, a second cladding layer, one or more waveguides having a waveguide core and an air-gap cladding layer engaging a portion of waveguide core, wherein the first cladding layer and the second cladding layer engage the waveguide.
    Type: Application
    Filed: December 11, 2003
    Publication date: July 1, 2004
    Inventors: Tony Mule, James D. Meindl, Paul Kohl, Stephen M. Schultz, Thomas K. Gaylord, Elias N. Glytsis, Ricardo Villalaz, Muhannad Bakir, Hollie Reed
  • Publication number: 20040071387
    Abstract: Systems and methods for back-of-die, through-wafer guided-wave optical clock distribution systems (networks) are disclosed. A representative back-of-die, through-wafer guided-wave optical clock distribution system includes an integrated circuit device with a first cladding layer disposed on the back-side of the integrated circuit device, and an core layer disposed on the first cladding layer. The core layer, the first cladding layer, or the second cladding layer can include, but is not limited to, vertical-to-horizontal input diffraction gratings, a horizontal-to-horizontal diffraction gratings, and horizontal-to-vertical output diffraction gratings.
    Type: Application
    Filed: July 30, 2003
    Publication date: April 15, 2004
    Inventors: Tony Mule, James D. Meindl, Thomas K. Gaylord
  • Publication number: 20040017215
    Abstract: Optoelectronic probe cards, methods of fabrication, and methods of use, are disclosed. Briefly described, one exemplary embodiment includes an optoelectronic probe card adapted to test an electrical quality and an optical quality of an optoelectronic structure under test having electrical and optical components.
    Type: Application
    Filed: March 17, 2003
    Publication date: January 29, 2004
    Inventors: Tony Mule, Hiren Thacker, Muhannad Bakir, James D. Meindl, Thomas K. Gaylord, Kevin P. Martin, Paul Kohn
  • Publication number: 20030012539
    Abstract: Optical interconnect layers and methods of fabrication thereof are described. In addition, the optical interconnect layers integrated into devices such as backplane (BP), printed wiring board (PWB), and multi-chip module (MCM) level devices are described. A representative optical interconnect layer includes a first cladding layer, a second cladding layer, one or more waveguides having a waveguide core and an air-gap cladding layer engaging a portion of waveguide core, wherein the first cladding layer and the second cladding layer engage the waveguide.
    Type: Application
    Filed: April 29, 2002
    Publication date: January 16, 2003
    Inventors: Tony Mule', James D. Meindl, Paul Kohl, Stephen M. Schultz, Thomas K. Gaylord, Elias N. Glytsis, Ricardo Villalaz, Muhannad Bakir, Hollie Reed
  • Publication number: 20020186950
    Abstract: Waveguides and methods of fabrication thereof are presented. A representative waveguide includes a waveguide core and a cladding layer, where the cladding layer surrounds the waveguide core. The waveguide core and cladding can be made of a host material having a plurality of nano-pores, wherein the nano-pores include a sacrificial material, and the sacrificial material can be selectively decomposed in both the core and cladding layers to form a plurality of nano air-gaps.
    Type: Application
    Filed: May 10, 2002
    Publication date: December 12, 2002
    Inventors: Tony Mule', Paul Kohl, James D. Meindl, Agnes Padovani, Thomas K. Gaylord, Elias N. Glytsis, Sue Ann B. Allen
  • Publication number: 20020136481
    Abstract: Wafer-level electronic packages having waveguides and methods of fabricating chip-level electronic packages having waveguides are disclosed. A representative chip-level electronic package includes at least one waveguide having a waveguide core. In addition, another representative chip-level electronic package includes a waveguide having an air-gap cladding layer around a portion of the waveguide core. A representative method for fabricating a chip-level electronic package includes: providing a substrate having a passivation layer disposed on the substrate; disposing a waveguide core on a portion of the passivation layer; disposing a first sacrificial layer onto at least one portion of the passivation layer and the waveguide core; disposing an overcoat layer onto the passivation layer and the first sacrificial layer; and removing the first sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and around a portion of the waveguide core.
    Type: Application
    Filed: February 11, 2002
    Publication date: September 26, 2002
    Inventors: Tony Mule', Chirag Patel, James D. Meindl, Thomas K. Gaylord, Elias N. Glytsis, Kevin P. Martin, Stephen M. Schultz, Muhannad Bakir, Hollie Reed, Paul Kohl
  • Publication number: 20020122648
    Abstract: Waveguides having air-gap cladding layers and methods of fabricating waveguides having air-gap cladding layers are disclosed. A representative waveguide includes a waveguide core having an air-gap cladding layer engaging a portion of the waveguide core. In addition, a representative method of fabricating a waveguide having an air-gap cladding layer includes: providing a substrate having a lower cladding layer disposed on the substrate; disposing a waveguide core on a portion of the lower cladding layer; disposing a sacrificial layer onto at least one portion of the lower cladding layer and the waveguide core; disposing an overcoat layer onto the lower cladding layer and the sacrificial layer; and removing the sacrificial layer to define an air-gap cladding layer within the overcoat polymer layer and engaging a portion of the waveguide core.
    Type: Application
    Filed: February 11, 2002
    Publication date: September 5, 2002
    Applicant: Georgia Tech Research Corporation
    Inventors: Tony Mule', James D. Meindl, Thomas K. Gaylord, Elias N. Glytsis, Paul Kohl