Patents by Inventor Tony Phan
Tony Phan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180076038Abstract: A method of fabricating an integrated circuit includes forming a patterned dielectric layer, which includes a first pattern of openings, over a substrate and implanting a first n-type dopant into the substrate through the patterned dielectric layer to form a first doped region. The method continues with forming a patterned photoresist layer overlying the patterned dielectric layer, which includes a second pattern of openings and implanting a second n-type dopant into the substrate through the patterned photoresist layer and patterned dielectric layer to form a second doped region. The patterned photoresist layer and patterned dielectric layer are removed. An epitaxial layer is grown on the substrate and the first doped region and second doped region are driven into said epitaxial layer to form respective first and second n-type buried layers, then active devices are formed in the epitaxial layer.Type: ApplicationFiled: September 9, 2016Publication date: March 15, 2018Inventors: Tony Phan, Billy Alan Wofford
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Patent number: 8250116Abstract: A data simulator receives a set of directives specified in a file and creates one or more datastreams from which a data structure may be built as specified by the directives. The directives may specify configuration settings, constants, changing fields, values and probabilities.Type: GrantFiled: December 31, 2008Date of Patent: August 21, 2012Assignee: Unisys CorporationInventors: Jane C. Mazzagatti, Tony Phan
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Patent number: 8010572Abstract: A scenario simulator processor receives a declarative file and invokes one or more data simulators to create one or more datastreams from a data structure may be built as specified by the declarative file. The declarative file may specify one or more scenario names, and a set of information corresponding to the one or more scenarios (one set for each scenario). Each set of scenario information includes one or more of the following pieces of information: parameters and settings for the data simulator and the number of threads to be started for each data simulator invoked.Type: GrantFiled: November 16, 2007Date of Patent: August 30, 2011Assignee: Unisys CorporationInventors: Jane C. Mazzagatti, Tony Phan
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Patent number: 7838429Abstract: A method for manufacturing a semiconductor device that method comprises forming a thin film resistor by a process that includes depositing a resistive material layer on a semiconductor substrate. The process also includes depositing an insulating layer on the resistive material layer, and performing a first dry etch process on the insulating layer to form an insulative body. The process further includes performing a second dry etch process on the resistive material layer to form a resistive body. The resistive body and the insulative body have substantially identical perimeters.Type: GrantFiled: July 18, 2007Date of Patent: November 23, 2010Assignee: Texas Instruments IncorporatedInventors: Tony Phan, Kyle M. Flessner, Martin B. Mollat, Connie Wang, Arthur Pan, Eric William Beach, Michelle R. Keramidas, Karen Elizabeth Burks
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Publication number: 20100169384Abstract: A data simulator receives a set of directives specified in a file and creates one or more datastreams from which a data structure may be built as specified by the directives. The directives may specify configuration settings, constants, changing fields, values and probabilities.Type: ApplicationFiled: December 31, 2008Publication date: July 1, 2010Inventors: Jane C. Mazzagatti, Tony Phan
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Publication number: 20100169370Abstract: The KStore or K is a datastore made up of a forest of interconnected, highly unconventional trees of one or more levels. A KStore event manager monitors events and polls for KStore state. When triggered by user-defined conditions or receiving notification that a specified event has occurred, a specified response can be executed. An event/condition/response is defined through a KStore event wizard. When a triggering condition is detected or a notification of an event is received, a user-defined action or sequence of actions is performed automatically, without further user interaction.Type: ApplicationFiled: December 31, 2008Publication date: July 1, 2010Inventors: Jane C. Mazzagatti, Tony Phan
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Publication number: 20090023263Abstract: A method for manufacturing a semiconductor device that method comprises forming a thin film resistor by a process that includes depositing a resistive material layer on a semiconductor substrate. The process also includes depositing an insulating layer on the resistive material layer, and performing a first dry etch process on the insulating layer to form an insulative body. The process further includes performing a second dry etch process on the resistive material layer to form a resistive body. The resistive body and the insulative body have substantially identical perimeters.Type: ApplicationFiled: July 18, 2007Publication date: January 22, 2009Applicant: Texas Instruments IncorporatedInventors: Tony Phan, Kyle M. Flessner, Martin B. Mollat, Connie Wang, Arthur Pan, Eric William Beach, Michelle R. Keramidas, Karen Elizabeth Burks
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Publication number: 20070102017Abstract: A cigarette and cigarette paper have a plurality of multilayer bands formed by printing a highly viscous aqueous film-forming composition. After heating the composition to lower its viscosity, the bands are applied to the cigarette paper by gravure printing the composition. The composition is quenched and gelatinized by contact with the cool cigarette paper reducing absorption of water by the paper and reducing wrinkling, cockling, and waviness. Multiple gravure printed layers may be used to form the bands.Type: ApplicationFiled: August 9, 2006Publication date: May 10, 2007Inventors: Timothy Sherwood, Firooz Rasouli, Ping Li, Don Miser, Joe Mohajer, Bruce Waymack, Tony Phan, Tracy Madison, John Tilley, Yezdi Pithawalla
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Publication number: 20070045732Abstract: The present invention provides an integrated circuit and a method of manufacture therefor. The integrated circuit (100), in one embodiment without limitation, includes a dielectric layer (120) located over a wafer substrate (110), and a semiconductor substrate (130) located over the dielectric layer (120), the semiconductor substrate (130) having one or more transistor devices (160) located therein or thereon. The integrated circuit (100) may further include an interconnect (180) extending entirely through the semiconductor substrate (130) and the dielectric layer (120), thereby electrically contacting the wafer substrate (110), and one or more isolation structures (150) extending entirely through the semiconductor substrate (130) to the dielectric layer (120).Type: ApplicationFiled: August 3, 2005Publication date: March 1, 2007Applicant: Texas Instruments Inc.Inventors: John Lin, Tony Phan, Philip Hower, William Loftin, Martin Mollat
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Publication number: 20070029611Abstract: The present invention provides an integrated circuit and a method of manufacture therefore. The integrated circuit (100, 1000), in one embodiment without limitation, includes a dielectric layer (120, 1020) located over a wafer substrate (110, 1010), and a semiconductor substrate (130, 1030) located over the dielectric layer (120, 1020), the semiconductor substrate (130, 1030) having one or more transistor devices (140, 1040) located therein or thereon. The integrated circuit (100, 1000) may further include an interconnect (170, 1053) extending entirely through the semiconductor substrate (130, 1030) and the dielectric layer (120, 1020), thereby electrically contacting the wafer substrate (110, 1010).Type: ApplicationFiled: August 2, 2005Publication date: February 8, 2007Applicant: Texas Instruments IncorporatedInventors: Tony Phan, William Loftin, John Lin, Philip Hower
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Publication number: 20060197134Abstract: The present invention provides a method for manufacturing a metal-insulator-metal (MIM) capacitor, a method for manufacturing an integrated circuit having a metal-insulator-metal (MIM) capacitor, and an integrated circuit having a metal-insulator-metal (MIM) capacitor. The method for manufacturing the metal-insulator-metal (MIM) capacitor, among other steps and without limitation, includes providing a material layer (185) over a substrate (110), and forming a refractory metal layer (210) having a thickness (t1) over the substrate (110), at least a portion of the refractory metal layer (210) extending over the material layer (185). The method further includes reducing the thickness (t2) of the portion of the refractory metal layer (210) extending over the material layer (185), thereby forming a thinned refractory metal layer (310), and reacting the thinned refractory metal layer (310) with at least a portion of the material layer (185) to form an electrode (440) for use in a capacitor.Type: ApplicationFiled: March 3, 2005Publication date: September 7, 2006Applicant: Texas Instruments, Inc.Inventors: Tony Phan, Martin Mollat
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Publication number: 20060171221Abstract: The present invention provides a method for analyzing critical defects in analog integrated circuits. The method for analyzing critical defects, among other possible steps, may include fault testing a power field effect transistor (120) portion of an analog integrated circuit (115) to obtain electrical failure data. The method may further include performing an in-line optical inspection of the analog integrated circuit (115) to obtain physical defect data, and correlating the electrical failure data and physical defect data to analyze critical defects.Type: ApplicationFiled: January 31, 2005Publication date: August 3, 2006Applicant: Texas Instruments, Inc.Inventors: Martin Mollat, Milind Khandekar, Tony Phan, Kyle Flessner
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Publication number: 20060128109Abstract: The present invention provides method of manufacturing a metal-insulator-metal capacitor (100). A method of manufacturing includes depositing a first refractory metal layer (105) over a semiconductor substrate (110). The first refractory metal layer (105) over a capacitor region (200) of the semiconductor substrate (110) is removed and a second refractory metal (300) is deposited over the capacitor region (200). Other aspects of the present invention include a metal-insulator-metal capacitor (900) and a method of manufacturing an integrated circuit (1000).Type: ApplicationFiled: February 13, 2006Publication date: June 15, 2006Inventors: Tony Phan, Farris Malone
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Publication number: 20060101048Abstract: A data analysis system for performing an analytic to obtain an analytic result in a computing device having memory including a data analyzer interface, at least one interlocking trees datastore within the associated memory, and at least one analytic application executed. The data analysis system of the invention also includes a plurality of interlocking trees datastores wherein the at least one interlocking trees datastore is selected from the plurality of interlocking trees datastores in accordance with the data analyzer interface. The system can include a plurality of data sources wherein the at least one interlocking trees datastore is created from a data source selected from the plurality of data sources in accordance with the data analyzer interface. The at least one interlocking trees datastore further can be a static interlocking trees datastore or a dynamic interlocking trees datastore. The at least one interlocking trees datastore continuously records new data.Type: ApplicationFiled: August 26, 2005Publication date: May 11, 2006Inventors: Jane Mazzagatti, Jane Claar, Tony Phan, Haig Didizian
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Publication number: 20060100845Abstract: A method for generating data for a KStore includes collecting modeled process defining parameters to provide a defined modeled process and instantiating a first simulator. A data stream is created by the simulator in accordance with the defined modeled process and a data stream is transmitted to a data storage device. Executing a single thread and executing a plurality of threads by the first simulator are set forth. A single set of modeled process defining parameters is collected. A data stream of the single modeled process is provided in accordance with the single set of modeled process defining parameters. A second simulator can be instantiated and a single thread or a plurality of threads can be executed on the second simulator. A plurality of sets of modeled process defining parameters is collected and a plurality data streams of the modeled processes are provided in accordance with the plurality of sets of modeled process defining parameters.Type: ApplicationFiled: April 14, 2005Publication date: May 11, 2006Inventors: Jane Mazzagatti, Tony Phan
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Publication number: 20060040459Abstract: A method of fabricating a thin film resistor (100) without a hardmask or resistor head. The resistor material (104), e.g., NiCr, is deposited. The resistor material (104) is patterned and sputter etched to form the resistor body without first depositing a hardmask material. For example, a sputter etch chemistry comprising BCl3, Cl2, and Ar may be used to etch the resistor material.Type: ApplicationFiled: August 19, 2004Publication date: February 23, 2006Inventors: Tony Phan, Daniel Tsai
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Publication number: 20060040458Abstract: A method of fabricating a thin film resistor (100). The resistor material (104), e.g., NiCr, is deposited. A hard mask material (106), e.g., TiW, may be deposited over the resistor material (104). The resistor material (104) and hard mask material (106) are patterned and sputter etched to form the resistor body. For example, a sputter etch chemistry comprising BCl3, Cl2, and Ar may be used to etch the resistor material.Type: ApplicationFiled: August 19, 2004Publication date: February 23, 2006Inventors: Tony Phan, Daniel Tsai
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Publication number: 20060019460Abstract: The present invention provides method of manufacturing a metal-insulator-metal capacitor (100). A method of manufacturing includes depositing a first refractory metal layer (105) over a semiconductor substrate (110). The first refractory metal layer (105) over a capacitor region (200) of the semiconductor substrate (110) is removed and a second refractory metal (300) is deposited over the capacitor region (200). Other aspects of the present invention include a metal-insulator-metal capacitor (900) and a method of manufacturing an integrated circuit (1000).Type: ApplicationFiled: July 20, 2004Publication date: January 26, 2006Applicant: Texas Instruments IncorporatedInventors: Tony Phan, Farris Malone
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Publication number: 20050221571Abstract: An embodiment of the invention is a Schottky diode 22 having a semiconductor substrate 3, a first metal 24, a barrier layer 26, and second metal 28. Another embodiment of the invention is a method of manufacturing a Schottky diode 22 that includes providing a semiconductor substrate 3, forming a barrier layer 26 over the semiconductor substrate 3, forming a first metal layer 23 over the semiconductor substrate 3, annealing the semiconductor substrate 3 to form areas 24 of reacted first metal and areas 23 of un-reacted first metal, and removing selected areas 23 of the un-reacted first metal.Type: ApplicationFiled: March 30, 2004Publication date: October 6, 2005Inventors: Richard Irwin, Tony Phan, Hong-Ryong Kim, Ming-Yeh Chuang, Jennifer Dumin, Patrick Jones, Fredric Bailey
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Publication number: 20050218433Abstract: An embodiment of the invention is a Schottky diode 22 having a semiconductor substrate 3, a first metal 24, a barrier layer 26, and second metal 28. Another embodiment of the invention is a method of manufacturing a Schottky diode 22 that includes providing a semiconductor substrate 3, forming a barrier layer 26 over the semiconductor substrate 3, forming a first metal layer 23 over the semiconductor substrate 3, annealing the semiconductor substrate 3 to form areas 24 of reacted first metal and areas 23 of un-reacted first metal, and removing selected areas 23 of the un-reacted first metal. The method further includes forming a second metal layer 30 over the semiconductor substrate 3 and annealing the semiconductor substrate 3 to form areas 28 of reacted second metal and areas 30 of un-reacted second metal.Type: ApplicationFiled: March 30, 2005Publication date: October 6, 2005Inventors: Richard Irwin, Tony Phan, Hong-Ryong Kim, Ming-Yeh Chuang, Jennifer Dumin, Patrick Jones