Patents by Inventor Tony QIAN

Tony QIAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11563407
    Abstract: The present disclosure provides a mixing circuit with high harmonic suppression ratio, including: a multi-phase generation module, which receives a first input signal and generates eight first square wave signals with a phase difference of 45°; a quadrature phase generation module, which receives a second input signal and generates four second square wave signals with a phase difference of 90°; a harmonic suppression module, connected with an output end of the quadrature phase generation module to filter out higher order harmonic components in the second square wave signals; and a mixing module, connected with output ends of the multi-phase generation module and the harmonic suppression module to mix output signals of the multi-phase generation module and the harmonic suppression module. The mixing circuit with high harmonic suppression ratio adds a harmonic suppression module on the basis of multi-phase mixing, thereby improving the harmonic suppression ratio of the output signal.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: January 24, 2023
    Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.
    Inventors: Yu Li, Peng Ma, Yi Zeng, Shenglei Wang, Tony Qian
  • Patent number: 11159254
    Abstract: The present disclosure provides an automatic mismatch calibration circuit and method, and a radio frequency receiver system. The automatic mismatch calibration circuit includes: at least one direct current (DC) offset estimation and calibration module coupled to a rear end of a radio frequency (RF) receiver to estimate a DC offset of received signals transmitted in an I channel and a Q channel to obtain an I-channel-DC-component and a Q-channel-DC-component, and compensate the I-channel-DC-component and the Q-channel-DC-component to the received signals corresponding to the I channel and the Q channel to achieve DC offset calibration. The present disclosure solves the problem that the existing mismatch calibration circuit cannot meet the low power consumption requirements of the system.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: October 26, 2021
    Assignees: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.
    Inventors: Tingwen Xiong, Yi Zeng, Tony Qian
  • Publication number: 20210281218
    Abstract: The present disclosure provides a mixing circuit with high harmonic suppression ratio, including: a multi-phase generation module, which receives a first input signal and generates eight first square wave signals with a phase difference of 45°; a quadrature phase generation module, which receives a second input signal and generates four second square wave signals with a phase difference of 90°; a harmonic suppression module, connected with an output end of the quadrature phase generation module to filter out higher order harmonic components in the second square wave signals; and a mixing module, connected with output ends of the multi-phase generation module and the harmonic suppression module to mix output signals of the multi-phase generation module and the harmonic suppression module. The mixing circuit with high harmonic suppression ratio adds a harmonic suppression module on the basis of multi-phase mixing, thereby improving the harmonic suppression ratio of the output signal.
    Type: Application
    Filed: September 30, 2020
    Publication date: September 9, 2021
    Applicants: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.
    Inventors: Yu LI, Peng MA, Yi ZENG, Shenglei WANG, Tony QIAN
  • Publication number: 20210143920
    Abstract: The present disclosure provides an automatic mismatch calibration circuit and method, and a radio frequency receiver system. The automatic mismatch calibration circuit includes: at least one direct current (DC) offset estimation and calibration module coupled to a rear end of a radio frequency (RF) receiver to estimate a DC offset of received signals transmitted in an I channel and a Q channel to obtain an I-channel-DC-component and a Q-channel-DC-component, and compensate the I-channel-DC-component and the Q-channel-DC-component to the received signals corresponding to the I channel and the Q channel to achieve DC offset calibration. The present disclosure solves the problem that the existing mismatch calibration circuit cannot meet the low power consumption requirements of the system.
    Type: Application
    Filed: September 30, 2020
    Publication date: May 13, 2021
    Applicants: VeriSilicon Microelectronics (Shanghai) Co., Ltd., VeriSilicon Holdings Co., Ltd.
    Inventors: Tingwen XIONG, Yi ZENG, Tony QIAN