Abstract: A medical system and method for estimating a treatment region for a medical treatment device is provided. The system includes a memory; a processor coupled to the memory; and a treatment control module stored in the memory and executable by the processor. The treatment control module generates an estimated treatment region which is an estimate of a treatment region which would have been derived as a result of a numerical model analysis such as a finite element analysis. Advantageously, the estimated treatment region is generated using a fraction of the time it takes to generate the region using the numerical model analysis.

Abstract: A system and method for interactively planning and controlling a treatment of a patient for a medical treatment device are provided. The system includes a memory; a processor coupled to the memory; and a treatment control module stored in the memory and executable by the processor. The treatment control module graphically displays in real time a continuously changing treatment region defined by the electrodes as a user moves at least one of the electrodes. This allows the user to more effectively plan and treat a target region.

Abstract: A logic analysis subsystem in a time-sliced emulator. The logic analysis subsystem "reconstructs" signals that were previously reduced by the compiler and allows the user to set breakpoints and triggers using these and other signals of the emulated circuit. The present invention includes a "logic analysis subsystem compiler" and "logic analysis subsystem hardware." The logic analysis subsystem compiler is either a subpart of the regular emulator compiler or is a standalone compiler. It compiles the design to be emulated and generates control instructions for the logic analysis subsystem hardware. The logic analysis subsystem hardware is incorporated into the time-sliced emulator to receive signals generated by the emulator during emulation. When the logic analysis subsystem operates, the control instructions cause the logic analysis subsystem to reconstruct previously reduced signals received from the emulator.

Abstract: A time-sliced hardware-based emulator including at least one of: programmable I/O assignment; programmable levels of DC voltage; programmable pull-up or pull-down resistors in the emulator on a pin-by pin basis; programmable forcing and/or disabling of value output from the emulator on each pin; programmable clocking; and programmable sample modes. An emulator is connected to a target system via a Pod System Interface (PSI), a specially designed cable, and a Pod User Interface (PUI). For data traveling from the emulator to the target system, each PSI receives up to 128 bits of data from the emulator. The cable, however, is only 32 bits wide. Therefore, the emulator multiplexes the data sent over the cable, sending eight interleaved groups of 32 bits to the PSI in accordance with a fast clock signal. Each PUI receives the groups of 32 bits from the PSI and sends them to the target system in accordance with control signals from the emulator.

Abstract: A system and method for emulating memory designs is described. The system includes a time sliced logic emulator. The time sliced logic emulator emulates the functions performed in one cycle of a target design by emulating portions of the functions in a set of time slices. That is, a set of time slices represents a single clock cycle in the target design. The system emulates many different types of memory designs included in the target design. The system includes an emulation memory. The memory designs are mapped to the emulation memory via a programmable address generation block. For a given time slice, the programmable address generation block generates an address that maps all or part of a memory design address to an emulation memory address. The programmable address generation block allows multiple memory designs to be mapped to a single emulation memory and allows a single memory design to be mapped to multiple emulation memories.