Patents by Inventor Tony Shaberman

Tony Shaberman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6055593
    Abstract: The miniature card uses an Attribute Information Structure (AIS) for card recognition. The PC Card specification uses a Card Information Structure (CIS) for card recognition. The dual information structure definition provides a mechanism to allow a miniature card to be recognized and functional in both a PC Card environment and miniature card environment. The dual information structure mechanism incorporates the AIS structure into the CIS structure within the miniature card, thus allowing a card to be recognized and function in both environments.
    Type: Grant
    Filed: December 31, 1996
    Date of Patent: April 25, 2000
    Assignee: Intel Corporation
    Inventors: Tony Shaberman, Thomas Newman, Sean Casey
  • Patent number: 5938750
    Abstract: An apparatus and method for a memory card bus design. The memory card bus design allows the memory card to interface with a wide variety of systems such as, hand held consumer products and personal computers. The bus design provides a simple interface for both volatile and non-volatile memories which allows data to be exchanged between the memory device and another system.
    Type: Grant
    Filed: June 28, 1996
    Date of Patent: August 17, 1999
    Assignee: Intel Corporation
    Inventor: Tony Shaberman
  • Patent number: 5761732
    Abstract: A method and apparatus for interfacing a memory card with a system having a smaller bus width while maintaining its interchangeability with other systems having larger bus widths. The host accesses data stored in the memory card using an interleaving scheme, such as a two-way interleaving scheme. The host provides a first enable signal and a second enable signal. In response to the first enable signal, data is accessed from a first section of the addressed memory location, and in response to the second enable signal, data is accessed from a second section of the addressed memory location. The first section of the addressed memory location may store even data bytes and the second section of the addressed memory location may store odd data bytes. The host may only access one section of the selected memory location at a time when using the interleaving scheme.
    Type: Grant
    Filed: June 28, 1996
    Date of Patent: June 2, 1998
    Assignee: Intel Corporation
    Inventors: Tony Shaberman, Sean Casey