Patents by Inventor Tony T Elappuparackal

Tony T Elappuparackal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data-driven clock gating for a sequential data-capture device
    Patent number: 7023240
    Abstract: A circuit for capturing data from a bus having a flip-flop register, comparison logic and clock logic. The comparison logic determines whether any bit on the bus has changed logic state. If a bit has changed state, the comparison logic asserts an enable signal which causes the clock logic to clock the register. Accordingly, data from the bus is not clocked through the register unless the data has actually changed state and the comparison logic itself determines whether different data is present on the bus.
    Type: Grant
    Filed: July 6, 2004
    Date of Patent: April 4, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Tony T Elappuparackal
  • Data-driven clock gating for a sequential data-capture device
    Publication number: 20040239367
    Abstract: A circuit for capturing data from a bus having a flip-flop register, comparison logic and clock logic. The comparison logic determines whether any bit on the bus has changed logic state. If a bit has changed state, the comparison logic asserts an enable signal which causes the clock logic to clock the register. Accordingly, data from the bus is not clocked through the register unless the data has actually changed state and the comparison logic itself determines whether different data is present on the bus.
    Type: Application
    Filed: July 6, 2004
    Publication date: December 2, 2004
    Inventor: Tony T. Elappuparackal
  • Data-driven clock gating for a sequential data-capture device
    Patent number: 6822478
    Abstract: A circuit for capturing data from a bus having a flip-flop register, comparison logic and clock logic. The comparison logic determines whether any bit on the bus has changed logic state. If a bit has changed state, the comparison logic asserts an enable signal which causes the clock logic to clock the register. Accordingly, data from the bus is not clocked through the register unless the data has actually changed state and the comparison logic itself determines whether different data is present on the bus.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: November 23, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Tony T. Elappuparackal
  • Data-driven clock gating for a sequential data-capture device
    Publication number: 20030006806
    Abstract: A circuit for capturing data from a bus having a flip-flop register, comparison logic and clock logic. The comparison logic determines whether any bit on the bus has changed logic state. If a bit has changed state, the comparison logic asserts an enable signal which causes the clock logic to clock the register. Accordingly, data from the bus is not clocked through the register unless the data has actually changed state and the comparison logic itself determines whether different data is present on the bus.
    Type: Application
    Filed: June 28, 2002
    Publication date: January 9, 2003
    Inventor: Tony T. Elappuparackal