Abstract: A method for storing data on a storage device includes receiving data to be stored and a logical address for storing the data. A physical address is determined and the data to be stored is stored at the determined physical address. A table that associates logical addresses with physical addresses is examined to determine a difference relationship between the determined physical address and a corresponding physical address for one of other logical addresses. Information representing the determined physical address is stored in the table, in association with the received logical address, as a function of the determined difference relationship. A data storage device includes controller circuitry and memory for storing a lookup table that associates logical addresses with physical addresses. The controller circuitry operates in accordance with the method.

Abstract: Aspects of the disclosure provide a circuit that includes a memory circuit and a controller circuit. The memory circuit is to have a look-up table (LUT) that associates logical address used in computation with physical address used in storage space. The LUT includes a first level LUT with first level entries corresponding to logical addresses, each first level entry includes an indicator field and a content field, and the indicator field is indicative of a compressible/non-compressible attribute of a physical address associated with a logical address. The controller circuit is to receive a logical address, and translate the logical address into a physical address associated with the logical address based on the LUT.

Abstract: A system including an encoder module, a buffer first-in first-out (FIFO) module, a buffer manager module, N FIFO modules, and N input/output (I/O) modules. The encoder module encodes data received from a host and generates P units of encoded data, where P is an integer greater than 1. The buffer FIFO module receives the P units from the encoder module and outputs the P units. The buffer manager module receives the P units from the buffer FIFO module, stores the P units in a buffer, retrieves N of the P units from the buffer, and outputs the N units in parallel, where N is an integer greater than 1. The N FIFO modules respectively receive the N units in parallel directly from the buffer manager. The N I/O modules receive the N units from the N FIFO modules in parallel, respectively, and output the N units to a storage medium.

Abstract: Devices, systems, methods, and other embodiments associated with accessing memory are described. In one embodiment, a method detects that a power quality associated with a volatile memory in a computing device meets a threshold value and in response thereto, reprogramming data from the volatile memory to a flash memory comprising multi-level cells. The reprogramming comprises: copying the data from the volatile memory, and writing the copied data: (1) to the most significant bits of the multi-level cells in the flash memory while skipping the least significant bits of the multi-level cells, or (2) to the least significant bits of the multi-level cells while skipping the most significant bits.

Abstract: In some implementations, a method includes receiving information in a storage device controller from one or more storage devices in a solid state drive system over one or more channels; and for information received over each of the one or more channels, determining whether a condition for sending the information received over the channel to a host device is satisfied, and sending the information received over the channel to the host device when the condition for sending the information is satisfied.

Abstract: In some implementations, an apparatus includes a first programmable hardware timer that specifies an initial wait time before issuing two or more commands to a storage device, and a second programmable hardware timer that specifies an interval time between at least two commands of the two or more commands.

Abstract: A storage drive includes a first integrated circuit, a second integrated circuit, an interface, an encoder, and a write module. The first integrated circuit includes a first array of memory cells. The second integrated circuit includes a second array of memory cells. The interface is connected to a host. The interface is configured to receive a first block of data transmitted from the host to the storage drive. The encoder is configured to encode the first block of data. The write module is configured to write (i) a first portion of the encoded first block of data to a first row of the first array of memory cells, and (ii) a second portion of the encoded first block of data to a first row of the second array of memory cells.

Abstract: Devices, systems, methods, and other embodiments associated with accessing memory are described. In one embodiment, a method detects that a power quality associated with a volatile memory in a computing device meets a threshold value and in response thereto, reprogramming data from the volatile memory to a flash memory comprising multi-level cells. The reprogramming comprises: copying the data from the volatile memory, and writing the copied data: (1) to the most significant bits of the multi-level cells in the flash memory while skipping the least significant bits of the multi-level cells, or (2) to the least significant bits of the multi-level cells while skipping the most significant bits.

Abstract: A system including an encoder module, a buffer first-in first-out (FIFO) module, a buffer manager module, N FIFO modules, and N input/output (I/O) modules. The encoder module encodes data received from a host and generates P units of encoded data, where P is an integer greater than 1. The buffer FIFO module receives the P units from the encoder module and outputs the P units. The buffer manager module receives the P units from the buffer FIFO module, stores the P units in a buffer, retrieves N of the P units from the buffer, and outputs the N units in parallel, where N is an integer greater than 1. The N FIFO modules respectively receive the N units in parallel directly from the buffer manager. The N I/O modules receive the N units from the N FIFO modules in parallel, respectively, and output the N units to a storage medium.

Abstract: Methods and systems for storing data in a memory system with different levels of redundancy are disclosed. Methods and systems consistent with the present invention provide allow a redundancy level to be associated with received data, wherein associating the redundancy level of the data includes determining a desired level of protection for that data and determining the redundancy level based on the desired level of protection. A zone within a memory system is located that has a redundancy level that matches the redundancy level of the data, and the data is stored in the located zone with the desired redundancy level.

Abstract: Systems and methods are provided for implementing various aspects of a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. If the decision-codeword corresponds to an inner code and an RS code is the outer code, a soft-information map can process the soft-information for the decision-codeword to produce soft-information for a RS decision-codeword. A RS decoder can employ the Berlekamp-Massey algorithm (BMA), list decoding, and a Chien search, and can include a pipelined architecture. A threshold-based control circuit can be used to predict whether list decoding will be needed and can suspend the list decoding operation if it predicts that list decoding is not needed.

Abstract: A storage drive includes a first integrated circuit, a second integrated circuit, an interface, an encoder, and a write module. The first integrated circuit includes a first array of memory cells. The second integrated circuit includes a second array of memory cells. The interface is connected to a host. The interface is configured to receive a first block of data transmitted from the host to the storage drive. The encoder is configured to encode the first block of data. The write module is configured to write (i) a first portion of the encoded first block of data to a first row of the first array of memory cells, and (ii) a second portion of the encoded first block of data to a first row of the second array of memory cells.

Abstract: In some implementations, an apparatus includes a first programmable hardware timer that specifies an initial wait time before issuing two or more commands to a storage device, and a second programmable hardware timer that specifies an interval time between at least two commands of the two or more commands.

Abstract: A hard disk controller (HDC) of a hard disk drive (HDD) includes an encoder module, a buffer manager module, N first-in first-out (FIFO) modules, and N read channel modules, where N is an integer greater than 1. The encoder module is configured to encode data received from a host and to generate P units of encoded data, where P is an integer greater than 1. The buffer manager module is configured to store the P units of encoded data in a buffer, retrieve N of the P units from the buffer, and output the N units in parallel. The N FIFO modules are configured to receive the N units in parallel from the buffer manager. The N read channel modules are configured to receive the N units from the N FIFO modules in parallel, respectively, and to output the N units to a magnetic medium of the HDD.

Abstract: Devices, systems, methods, and other embodiments associated with selectively accessing memory are described. In one embodiment, a method detects an indication indicative of whether to program fast access pages or slow access pages of a flash memory. In response to the detected indication, data is programmed from a volatile memory: (1) to the fast access pages of the flash memory while skipping the slow access pages, or (2) to the slow access pages while skipping the fast access pages.

Abstract: A method includes, in at least one aspect, asserting a control signal to one or more devices, determining an initial wait time after asserting the control signal, issuing a first command based on the initial wait time, determining a first interval time associated with the first command and a second command, and issuing the second command based on the first interval time.

Abstract: Systems and methods are provided for implementing list decoding in a Reed-Solomon (RS) error-correction system. A detector can provide a decision-codeword from a channel and can also provide soft-information for the decision-codeword. The soft-information can be organized into an order of combinations of error events for list decoding. An RS decoder can employ a list decoder that uses a pipelined list decoder architecture. The list decoder can include one or more syndrome modification circuits that can compute syndromes in parallel. A long division circuit can include multiple units that operate to compute multiple quotient polynomial coefficients in parallel. The list decoder can employ iterative decoding and a validity test to generate error indicators. The iterative decoding and validity test can use the lower syndromes.

Abstract: In some implementations, a method includes receiving commands from a host device, sending the commands to one or more flash memory devices, receiving information associated with at least one of the commands from the one or more flash memory devices, and selectively sending the information to the host device based on whether one or more parameters in the at least one command include a request to receive the information from the one or more flash memory devices.

Abstract: A method includes, in at least one aspect, asserting a control signal to one or more devices, determining an initial wait time after asserting the control signal, issuing a first command based on the initial wait time, determining a first interval time associated with the first command and a second command, and issuing the second command based on the first interval time.

Abstract: A system includes chips and a control module. Each of the chips includes an array of memory cells. Each of the arrays of memory cells includes rows of memory cells. Each of the rows of memory cells is configured to store a predetermined amount of data. The control module is configured to receive data, encode the data to generate blocks of encoded data, store a first portion of one of the blocks of encoded data in a first selected number row of a first chip, and store a remaining portion of the one of the blocks of encoded data in a second selected number row of a second chip. An amount of data in each of the blocks of encoded data is more than the predetermined amount of data. The second selected number row is a same number row or a higher number row than the first selected number row.