Patents by Inventor Tony Yuhsiang Cheng
Tony Yuhsiang Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9824772Abstract: A method of training chip select for a memory module. The method includes programming a memory controller into a mode wherein a command signal is active for a programmable time period. The method then programs a programmable delay line of the chip select with a delay value and performs initialization of the memory module. A read command is then sent to the memory module to toggle a state of the chip select. A number of data strobe signals sent by the memory module in response to the read command are counted. A determination is made whether the memory module is in a pass state or an error state based on a result of the counting.Type: GrantFiled: December 26, 2012Date of Patent: November 21, 2017Assignee: NVIDIA CORPORATIONInventors: Venkata Ramana Malladi, Tony Yuhsiang Cheng, Sharath Raghava, Ambuj Kumar, Arunjit Sahni, Paul Lam
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Patent number: 9607714Abstract: A method of training a command signal for a memory module. The method includes programming a memory controller into a mode where a single bit of an address signal is active for a single clock cycle. The method then programs a programmable delay line of the address signal with a delay value and performs initialization of the memory module. The memory module is then placed in a write leveling mode. A write leveling procedure is then performed and a response to the write leveling procedure is determined from the memory module. A determination is made whether the memory module is in a pass state or an error state based on the response.Type: GrantFiled: December 27, 2012Date of Patent: March 28, 2017Assignee: NVIDIA CORPORATIONInventors: Venkata Ramana Malladi, Tony Yuhsiang Cheng, Sharath Raghava, Ambuj Kumar, Arunjit Sahni, Paul Lam
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Patent number: 9378169Abstract: A method including sorting read/write commands initiated by a memory controller based upon a destination page within a memory device. The read/write commands having a highest priority level are determined. The commands are then categorized as either page movement commands or data movement commands. The page movement commands or data movement commands are sent to the memory device based upon a signal indicating a current direction of a data bus providing communication between the memory controller and the memory device and further based upon a priority level.Type: GrantFiled: December 31, 2012Date of Patent: June 28, 2016Assignee: NVIDIA CORPORATIONInventors: Ambuj Kumar, Brian Keith Langendorf, Sharath Raghava, Tony Yuhsiang Cheng
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Patent number: 9368169Abstract: A method of training chip select for a memory module. The method includes programming a memory controller into a mode wherein a command signal is active for a programmable time period. The method then programs a programmable delay line of the chip select with a delay value and performs initialization of the memory module. The memory module is then placed in a write leveling mode wherein placing the memory module in the write leveling mode toggles a state of the chip select. A write leveling procedure is then performed and a response thereto is determined from the memory module. A determination is made whether the memory module is in a pass state or an error state based on the response.Type: GrantFiled: December 26, 2012Date of Patent: June 14, 2016Assignee: NVIDIA CORPORATIONInventors: Venkata Ramana Malladi, Tony Yuhsiang Cheng, Sharath Raghava, Ambuj Kumar, Arunjit Sahni, Paul Lam
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Patent number: 9104421Abstract: A method for managing a memory controller comprising selecting a low-power state from a plurality of low-power states. The method further comprises transitioning to the low-power and entering the low-power state when the transition is complete, provided a wake-event has not been received. An apparatus comprises a controller configured to select a power state for transition, a state-machine configured to execute steps for transitions between power states of a memory controller connected by a bus to a memory, a storage configured to store at least one context, and a context engine configured to stream, at the direction of the state-machine engine, the at least one context to the memory controller. Streaming comprises communicating N portions of context data as a stream to N registers in the memory controller. A context comprises a plurality of calibrations corresponding to a state selected for transition.Type: GrantFiled: July 30, 2012Date of Patent: August 11, 2015Assignee: NVIDIA CORPORATIONInventors: Sagheer Ahmad, Edward L. Riegelsberger, Tony Yuhsiang Cheng, Laurent Rene Moll, Brian Keith Langendorf
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Publication number: 20140189180Abstract: A method including sorting read/write commands initiated by a memory controller based upon a destination page within a memory device. The read/write commands having a highest priority level are determined. The commands are then categorized as either page movement commands or data movement commands. The page movement commands or data movement commands are sent to the memory device based upon a signal indicating a current direction of a data bus providing communication between the memory controller and the memory device and further based upon a priority level.Type: ApplicationFiled: December 31, 2012Publication date: July 3, 2014Applicant: NVIDIA CORPORATIONInventors: Ambuj Kumar, Brian Keith Langendorf, Sharath Raghava, Tony Yuhsiang Cheng
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Publication number: 20140181392Abstract: A method of training chip select for a memory module. The method includes programming a memory controller into a mode wherein a command signal is active for a programmable time period. The method then programs a programmable delay line of the chip select with a delay value and performs initialization of the memory module. A read command is then sent to the memory module to toggle a state of the chip select. A number of data strobe signals sent by the memory module in response to the read command are counted. A determination is made whether the memory module is in a pass state or an error state based on a result of the counting.Type: ApplicationFiled: December 26, 2012Publication date: June 26, 2014Applicant: NVIDIA CORPORATIONInventors: Venkata Ramana Malladi, Tony Yuhsiang Cheng, Sharath Raghava, Ambuj Kumar, Arunjit Sahni, Paul Lam
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Publication number: 20140181429Abstract: A method of training a memory interface between a memory controller and a memory module. The method includes programming a delay line of a data strobe with a delay value and programming a reference voltage with a voltage value. The method then writes a data bit pattern to the memory module wherein the data bit pattern is of a first plurality of unique data bit patterns. The data bit pattern is read back and a result is compared with the data bit pattern. A determination is made whether the memory module is in a pass state or an error state based on the comparing. The steps are repeated with another data bit pattern of the first plurality of data bit patterns. The method is repeated for each combination of the data strobe delay value and the reference voltage value.Type: ApplicationFiled: December 26, 2012Publication date: June 26, 2014Applicant: NVIDIA CORPORATIONInventors: Venkata Ramana Malladi, Tony Yuhsiang Cheng, Ambuj Kumar, Brian Keith Langendorf
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Publication number: 20140181391Abstract: A method of training chip select for a memory module. The method includes programming a memory controller into a mode wherein a command signal is active for a programmable time period. The method then programs a programmable delay line of the chip select with a delay value and performs initialization of the memory module. The memory module is then placed in a write leveling mode wherein placing the memory module in the write leveling mode toggles a state of the chip select. A write leveling procedure is then performed and a response thereto is determined from the memory module. A determination is made whether the memory module is in a pass state or an error state based on the response.Type: ApplicationFiled: December 26, 2012Publication date: June 26, 2014Applicant: NVIDIA CORPORATIONInventors: Venkata Ramana Malladi, Tony Yuhsiang Cheng, Sharath Raghava, Ambuj Kumar, Arunjit Sahni, Paul Lam
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Publication number: 20140181451Abstract: A method of training a command signal for a memory module. The method includes programming a memory controller into a mode wherein a single bit of an address signal is active for a single clock cycle. The method then programs a programmable delay line of the address signal with a delay value and performs initialization of the memory module. The memory module is then placed in a write leveling mode. A write leveling procedure is then performed and a response thereto is determined from the memory module. A determination is made whether the memory module is in a pass state or an error state based on the response.Type: ApplicationFiled: December 27, 2012Publication date: June 26, 2014Applicant: NVIDIA CORPORATIONInventors: Venkata Ramana Malladi, Tony Yuhsiang Cheng, Sharath Raghava, Ambuj Kumar, Arunjit Sahni, Paul Lam
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Publication number: 20140181452Abstract: A method of training command signals for a memory module. The method includes programming a memory controller into a mode wherein a column access strobe is active for a single clock cycle. The method then programs a programmable delay line of the column access strobe with a delay value and performs initialization of the memory module. A read command is then sent to the memory module. A number of data strobe signals sent by the memory module in response to the read command are counted. A determination is made whether the memory module is in a pass state or an error state based on a result of the counting.Type: ApplicationFiled: December 27, 2012Publication date: June 26, 2014Applicant: NVIDIA CORPORATIONInventors: Venkata Ramana Malladi, Tony Yuhsiang Cheng, Sharath Raghava, Ambuj Kumar, Arunjit Sahni, Paul Lam
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Publication number: 20140032947Abstract: A method for managing a memory controller comprising selecting a low-power state from a plurality of low-power states. The method further comprises transitioning to the low-power and entering the low-power state when the transition is complete, provided a wake-event has not been received. An apparatus comprises a controller configured to select a power state for transition, a state-machine configured to execute steps for transitions between power states of a memory controller connected by a bus to a memory, a storage configured to store at least one context, and a context engine configured to stream, at the direction of the state-machine engine, the at least one context to the memory controller. Streaming comprises communicating N portions of context data as a stream to N registers in the memory controller. A context comprises a plurality of calibrations corresponding to a state selected for transition.Type: ApplicationFiled: July 30, 2012Publication date: January 30, 2014Applicant: NVIDIA CORPORATIONInventors: Sagheer Ahmad, Edward L. Riegelsberger, Tony Yuhsiang Cheng, Laurent Rene Moll, Brian Keith Langendorf
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Patent number: 8006062Abstract: A computing system has a mode of operation in which at least two different memory parameter profiles are read by a BIOS to configure memory. In one implementation the memory parameter profiles are stored in a serial presence detect memory using an extended serial presence detect format.Type: GrantFiled: May 9, 2008Date of Patent: August 23, 2011Assignee: Nvidia CorporationInventors: Tony Yuhsiang Cheng, Hon Fei Chong, Benjamin Dodge, Howard Tsai, Tsungyi Lin