Abstract: A semiconductor memory device includes a write data transfer unit; a plurality of groups of sense amplifiers; a plurality of word lines; and a plurality of pairs of bit lines. Each of the pairs of bit lines includes a pair of inside bit lines, extending between the write data transfer unit and each of the sense amplifiers, and a pair of outside bit lines, extending from each of the sense amplifiers to the side opposite the side of the write data transfer unit. A plurality of memory cells is connected between the word lines and the pairs of bit lines, respectively. The drive timing of a selected one of the groups of sense amplifiers, connected to the selected one of pairs of bit lines on which the transfer of the write data is being performed, is delayed when compared with the drive timing of the sense amplifiers connected to the remaining pairs of bit lines on which the transfer of the write data is not being performed.