Patents by Inventor Toon Ng
Toon Ng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12176327Abstract: An electronic package is provided, including: an encapsulation layer embedded with a first electronic component and conductive pillars; a circuit structure disposed on one surface of the encapsulation layer; a second electronic component disposed on the circuit structure; an insulation layer formed on the other surface of the encapsulation layer; and a circuit portion disposed on the insulation layer. Since the first and second electronic components are disposed on two sides of the circuit structure, respectively, the electronic package has various functions and high performance. A method for fabricating the electronic package is also provided.Type: GrantFiled: April 28, 2023Date of Patent: December 24, 2024Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Kong-Toon Ng, Hung-Ho Lee, Chee-Key Chung, Chang-Fu Lin, Chi-Hsin Chiu
-
Publication number: 20240019649Abstract: A semiconductor package includes a first mold layer at least partially encasing at least one photonic integrated circuit. A redistribution layer structure is fabricated on the first mold layer, the redistribution layer structure including dielectric material and conductive structures. A second mold layer at least partially encasing at least one semiconductor chip is fabricated on the redistribution layer structure. The redistribution layer structure provides electrical pathways between the at least one semiconductor chip and the at least one photonic integrated circuit. One or more voids are defined in the second mold layer in an area above an optical interface of the at least one photonic integrated circuit such that light is transmittable through dielectric material above the optical interface.Type: ApplicationFiled: July 24, 2023Publication date: January 18, 2024Inventors: BRETT P. WILKERSON, RAJA SWAMINATHAN, KONG TOON NG, RAHUL AGARWAL
-
Publication number: 20230268328Abstract: An electronic package is provided, including: an encapsulation layer embedded with a first electronic component and conductive pillars; a circuit structure disposed on one surface of the encapsulation layer; a second electronic component disposed on the circuit structure; an insulation layer formed on the other surface of the encapsulation layer; and a circuit portion disposed on the insulation layer. Since the first and second electronic components are disposed on two sides of the circuit structure, respectively, the electronic package has various functions and high performance. A method for fabricating the electronic package is also provided.Type: ApplicationFiled: April 28, 2023Publication date: August 24, 2023Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Kong-Toon Ng, Hung-Ho Lee, Chee-Key Chung, Chang-Fu LIN, Chi-Hsin Chiu
-
Patent number: 11709327Abstract: A semiconductor package includes a first mold layer at least partially encasing at least one photonic integrated circuit. A redistribution layer structure is fabricated on the first mold layer, the redistribution layer structure including dielectric material and conductive structures. A second mold layer at least partially encasing at least one semiconductor chip is fabricated on the redistribution layer structure. The redistribution layer structure provides electrical pathways between the at least one semiconductor chip and the at least one photonic integrated circuit. One or more voids are defined in the second mold layer in an area above an optical interface of the at least one photonic integrated circuit such that light is transmittable through dielectric material above the optical interface.Type: GrantFiled: June 28, 2021Date of Patent: July 25, 2023Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Brett P. Wilkerson, Raja Swaminathan, Kong Toon Ng, Rahul Agarwal
-
Publication number: 20230187364Abstract: An embodiment of a semiconductor chip device can include a molding layer having a first side and a second side, an interconnect chip at least partially encased in the molding layer, the interconnect chip comprising a through substrate via (TSV) that extends through the interconnect chip, an insulating layer positioned on the first side of the molding layer, and a conductive structure that is positioned vertically below the interconnect chip and extends through the insulating layer, wherein the conductive structure is electrically coupled to the TSV.Type: ApplicationFiled: December 14, 2021Publication date: June 15, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Chia-Hao Cheng, Kong Toon Ng, Rahul Agarwal, Brett P. Wilkerson
-
Patent number: 11676948Abstract: An electronic package is provided, including: an encapsulation layer embedded with a first electronic component and conductive pillars; a circuit structure disposed on one surface of the encapsulation layer; a second electronic component disposed on the circuit structure; an insulation layer formed on the other surface of the encapsulation layer; and a circuit portion disposed on the insulation layer. Since the first and second electronic components are disposed on two sides of the circuit structure, respectively, the electronic package has various functions and high performance. A method for fabricating the electronic package is also provided.Type: GrantFiled: June 3, 2021Date of Patent: June 13, 2023Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Kong-Toon Ng, Hung-Ho Lee, Chee-Key Chung, Chang-Fu Lin, Chi-Hsin Chiu
-
Publication number: 20220342165Abstract: A semiconductor package includes a first mold layer at least partially encasing at least one photonic integrated circuit. A redistribution layer structure is fabricated on the first mold layer, the redistribution layer structure including dielectric material and conductive structures. A second mold layer at least partially encasing at least one semiconductor chip is fabricated on the redistribution layer structure. The redistribution layer structure provides electrical pathways between the at least one semiconductor chip and the at least one photonic integrated circuit. One or more voids are defined in the second mold layer in an area above an optical interface of the at least one photonic integrated circuit such that light is transmittable through dielectric material above the optical interface.Type: ApplicationFiled: June 28, 2021Publication date: October 27, 2022Inventors: BRETT P. WILKERSON, RAJA SWAMINATHAN, KONG TOON NG, RAHUL AGARWAL
-
Patent number: 11418002Abstract: An electronic package and a method for fabricating an electronic package are provided. An encapsulation layer encapsulates a first electronic component and a plurality of conductive pillars, and is defined with a reservation region and a removal region adjacent to the reservation region. A circuit structure is disposed on the encapsulation layer. The removal region and the circuit structure therewithin are removed for an optical communication element to protrude from a lateral surface of the encapsulation layer when the optical communication element is disposed on the circuit structure, so as to avoid a packaging material used in a subsequent process from being adhered to a protruding portion of the optical communication element.Type: GrantFiled: October 31, 2019Date of Patent: August 16, 2022Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Kong-Toon Ng, Yi-Chian Liao
-
Patent number: 11289346Abstract: An electronic package and a method for fabricating the same are provided. The method includes: forming a circuit structure on an encapsulant; embedding a first electronic component and a plurality of conductive posts in the encapsulant; and disposing a second electronic component on the circuit structure. Since the first and second electronic components are arranged on opposite sides of the circuit structure, the electronic package can provide multi-function and high efficiency.Type: GrantFiled: July 2, 2020Date of Patent: March 29, 2022Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chen-Yu Huang, Chee-Key Chung, Chang-Fu Lin, Kong-Toon Ng, Rui-Feng Tai, Bo-Hao Ma
-
Publication number: 20210343546Abstract: An electronic package and a method for fabricating the same are provided. The electronic package includes a stepped recess formed at a peripheral portion of a packaging module to release stress of the electronic package.Type: ApplicationFiled: June 8, 2020Publication date: November 4, 2021Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Yung-Ta Li, Yi-Chian Liao, Kong-Toon Ng, Chang-Fu Lin
-
Patent number: 11164755Abstract: An electronic package and a method for fabricating the same are provided. The electronic package includes a stepped recess formed at a peripheral portion of a packaging module to release stress of the electronic package.Type: GrantFiled: June 8, 2020Date of Patent: November 2, 2021Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.Inventors: Yung-Ta Li, Yi-Chian Liao, Kong-Toon Ng, Chang-Fu Lin
-
Publication number: 20210296295Abstract: An electronic package is provided, including: an encapsulation layer embedded with a first electronic component and conductive pillars; a circuit structure disposed on one surface of the encapsulation layer; a second electronic component disposed on the circuit structure; an insulation layer formed on the other surface of the encapsulation layer; and a circuit portion disposed on the insulation layer. Since the first and second electronic components are disposed on two sides of the circuit structure, respectively, the electronic package has various functions and high performance. A method for fabricating the electronic package is also provided.Type: ApplicationFiled: June 3, 2021Publication date: September 23, 2021Inventors: Kong-Toon Ng, Hung-Ho Lee, Chee-Key Chung, Chang-Fu Lin, Chi-Hsin Chiu
-
Patent number: 11056470Abstract: An electronic package is provided, including: an encapsulation layer embedded with a first electronic component and conductive pillars; a circuit structure disposed on one surface of the encapsulation layer; a second electronic component disposed on the circuit structure; an insulation layer formed on the other surface of the encapsulation layer; and a circuit portion disposed on the insulation layer. Since the first and second electronic components are disposed on two sides of the circuit structure, respectively, the electronic package has various functions and high performance. A method for fabricating the electronic package is also provided.Type: GrantFiled: July 16, 2019Date of Patent: July 6, 2021Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Kong-Toon Ng, Hung-Ho Lee, Chee-Key Chung, Chang-Fu Lin, Chi-Hsin Chiu
-
Publication number: 20210066883Abstract: An electronic package and a method for fabricating an electronic package are provided. An encapsulation layer encapsulates a first electronic component and a plurality of conductive pillars, and is defined with a reservation region and a removal region adjacent to the reservation region. A circuit structure is disposed on the encapsulation layer. The removal region and the circuit structure therewithin are removed for an optical communication element to protrude from a lateral surface of the encapsulation layer when the optical communication element is disposed on the circuit structure, so as to avoid a packaging material used in a subsequent process from being adhered to a protruding portion of the optical communication element.Type: ApplicationFiled: October 31, 2019Publication date: March 4, 2021Inventors: Kong-Toon Ng, Yi-Chian Liao
-
Publication number: 20200402965Abstract: An electronic package is provided, including: an encapsulation layer embedded with a first electronic component and conductive pillars; a circuit structure disposed on one surface of the encapsulation layer; a second electronic component disposed on the circuit structure; an insulation layer formed on the other surface of the encapsulation layer; and a circuit portion disposed on the insulation layer. Since the first and second electronic components are disposed on two sides of the circuit structure, respectively, the electronic package has various functions and high performance. A method for fabricating the electronic package is also provided.Type: ApplicationFiled: July 16, 2019Publication date: December 24, 2020Inventors: Kong-Toon Ng, Hung-Ho Lee, Chee-Key Chung, Chang-Fu Lin, Chi-Hsin Chiu
-
Publication number: 20200335447Abstract: An electronic package and a method for fabricating the same are provided. The method includes: forming a circuit structure on an encapsulant; embedding a first electronic component and a plurality of conductive posts in the encapsulant; and disposing a second electronic component on the circuit structure. Since the first and second electronic components are arranged on opposite sides of the circuit structure, the electronic package can provide multi-function and high efficiency.Type: ApplicationFiled: July 2, 2020Publication date: October 22, 2020Inventors: Chen-Yu Huang, Chee-Key Chung, Chang-Fu Lin, Kong-Toon Ng, Rui-Feng Tai, Bo-Hao Ma
-
Patent number: 10741500Abstract: An electronic package and a method for fabricating the same are provided. The method includes: forming a circuit structure on an encapsulant; embedding a first electronic component and a plurality of conductive posts in the encapsulant; and disposing a second electronic component on the circuit structure. Since the first and second electronic components are arranged on opposite sides of the circuit structure, the electronic package can provide multi-function and high efficiency.Type: GrantFiled: May 4, 2018Date of Patent: August 11, 2020Assignee: Siliconware Precision Industries Co., Ltd.Inventors: Chen-Yu Huang, Chee-Key Chung, Chang-Fu Lin, Kong-Toon Ng, Rui-Feng Tai, Bo-Hao Ma
-
Publication number: 20190237374Abstract: An electronic package and a method for fabricating the same are provided. The method includes: forming a circuit structure on an encapsulant; embedding a first electronic component and a plurality of conductive posts in the encapsulant; and disposing a second electronic component on the circuit structure. Since the first and second electronic components are arranged on opposite sides of the circuit structure, the electronic package can provide multi-function and high efficiency.Type: ApplicationFiled: May 4, 2018Publication date: August 1, 2019Inventors: Chen-Yu Huang, Chee-Key Chung, Chang-Fu Lin, Kong-Toon Ng, Rui-Feng Tai, Bo-Hao Ma
-
Publication number: 20050118290Abstract: Compositions and method for treatment of steroid/nuclear receptor-mediated diseases. The present invention relates to non-aqueous extracts of Astragalus Membranaceus (HQ) and to compositions thereof. Also provided is a method for the treatment of PPAR-mediated physiological conditions comprising administering to a subject an effective amount of at least one of the above mentioned extracts and also a method for augmenting or synergising the activity of ligands of steroid/nuclear receptors comprising administering to a subject an effective amount of at least one of: an extract of Astragalus Membranaceus (HQ) or a flavonoid compound; in the presence of at least one ligand of steroid/nuclear receptors.Type: ApplicationFiled: December 2, 2003Publication date: June 2, 2005Applicant: University of SingaporeInventors: Eu Leong Yong, Toon Ng, Ping Shen, Wan Heng, Yinhan Gong