Abstract: A semiconductor storage device according to the present embodiment includes a semiconductor substrate. Each of memory cell arrays includes a plurality of memory cells on the semiconductor substrate. Select gate transistors are provided on ends of the memory cell arrays and brought into conduction when the memory cells are connected to a corresponding line. An embedded impurity layer is embedded in active areas between the select gate transistors respectively corresponding to the memory cell arrays adjacent to each other. Contact plugs connect the embedded impurity layer and the lines.

Abstract: A semiconductor storage device according to the present embodiment includes a semiconductor substrate. Each of memory cell arrays includes a plurality of memory cells on the semiconductor substrate. Select gate transistors are provided on ends of the memory cell arrays and brought into conduction when the memory cells are connected to a corresponding line. An embedded impurity layer is embedded in active areas between the select gate transistors respectively corresponding to the memory cell arrays adjacent to each other. Contact plugs connect the embedded impurity layer and the lines.

Abstract: A semiconductor device includes a semiconductor substrate divided into a memory cell region in which a memory cell is formed and a peripheral circuit region in which a peripheral circuit for driving the memory cell is formed, a plurality of conductive layers provided in each region so as to interpose an interlayer insulating film, a plurality of connection wiring layers formed in a plurality of holes which are formed in the interlayer insulating film so as to extend through the conductive layers of each region, the connection wiring layers electrically connecting the conductive layers, and a spacer insulating film functioning as a spacer which is formed on inner sidewall surfaces of the holes and outer sidewall surfaces of the connection wiring layers in each region.

Abstract: A semiconductor device includes a semiconductor substrate, a gate insulating film, gate electrodes, a first silicon oxide film, bit lines formed on the first silicon oxide film and including lower surfaces having respective recesses, a contact plug layer located between the gate electrodes and including a first portion, a second portion having a fourth side surface between the opposed second side surfaces of first silicon oxide film and a third portion having an upper surface and fifth side surfaces embedded in the respective recesses of the bit line, a first silicon nitride layer between a third side surface of the first portion of the contact plug and a first side surface of the gate electrode, and a second silicon oxide film. The entire upper surface and fifth side surface of the third portion of the contact plug directly contact with inner surfaces of the recesses respectively.

Abstract: A crack inspection device (6) for a concrete structure (1) includes: storage means for storing raster data obtained by imaging a surface (2) of the concrete structure (1) having a crack (3); conversion means for performing raster vector conversion on the data obtained by digitizing the raster data; data superimposing means for superimposing the vector data of the crack (3) obtained by the conversion means on the graphic data of the surface (2) of the concrete structure (1) while matching the coordinates; and output means for outputting the superimposed data obtained by the data superimposing means.

Abstract: An ultrasonic pulse is applied from a transmission probe for longitudinal waves kept in contact with the external surface of a concrete structure into the interior of the structure, and a reflected wave returning after being reflected by the boundary face of the concrete structure is detected with a reception probe for longitudinal waves kept in contact with the external surface of a concrete structure. As the first peak recognized in the waveform of the reflected wave represents the reaching time T1 of the bottom face echo which has undergone no mode conversion, and the subsequently obtained second peak, in about 1.3 to 1.7 times when first peak appeared, represents the reaching time T2 of the delayed echo which has undergone a mode conversion, the sonic velocity ratio R of longitudinal wave to transverse wave is calculated from these reaching times T1 and T2.

Abstract: A semiconductor device includes a semiconductor substrate divided into a memory cell region in which a memory cell is formed and a peripheral circuit region in which a peripheral circuit for driving the memory cell is formed, a plurality of conductive layers provided in each region so as to interpose an interlayer insulating film, a plurality of connection wiring layers formed in a plurality of holes which are formed in the interlayer insulating film so as to extend through the conductive layers of each region, the connection wiring layers electrically connecting the conductive layers, and a spacer insulating film functioning as a spacer which is formed on inner sidewall surfaces of the holes and outer sidewall surfaces of the connection wiring layers in each region.

Abstract: A semiconductor device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, an interlayer insulating film formed so that the gate electrode is buried therein, a contact hole formed in the interlayer insulating film so as to be adjacent to the gate electrode, the contact hole having a sidewall, a nitride film for the spacer formed on the sidewall of the contact hole and having a lower end, an insulating film interposed between the lower end of the spacer nitride film and a surface of the semiconductor substrate, and a conductor layer for the electrode formed so as to fill the contact hole.

Abstract: A semiconductor device comprising a lower conductive layer, an upper conductive layer located over the lower conductive layer, a first insulating film formed between upper and lower conductive layers, a plurality of connected wiring layers each of which has an upper surface, an upper side face and a sidewall outer periphery, each connected wiring layer being in structural contact with the upper conductive layer at the upper surface thereof and with the lower conductive layer, each connected wiring layer connecting the upper and lower conductive layers to each other, and a second insulating film formed on the sidewall outer periphery of each connected wiring layer so as to serve as a spacer between each connected wiring layer and the adjacent connected wiring layer, the second insulating film being made from a material differing from a material for the first insulating film.