Patents by Inventor Tooru Matsui

Tooru Matsui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240204179
    Abstract: Provided is a non-aqueous electrolyte secondary battery with enhanced discharging performance. A non-aqueous electrolyte secondary battery according to one aspect of the present disclosure is provided with an electrode having: a current collector; and a mixture layer that is formed on a surface of the current collector and that contains an active material, a conducting agent, and a binding agent. The mixture layer contains a first mixture layer facing the current collector and a second mixture layer laminated on a surface of the first mixture layer. A short-circuit resistance R1 of the first mixture layer and a short-circuit resistance R2 of the second mixture layer satisfy the relationship R1<R2.
    Type: Application
    Filed: April 12, 2022
    Publication date: June 20, 2024
    Applicant: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Tooru Matsui, Keisuke Asaka, Hirotetsu Suzuki, Motohiro Sakata, Kensuke Nakura
  • Publication number: 20240186530
    Abstract: Provided is a nonaqueous electrolyte secondary battery having improved discharge characteristics. A nonaqueous electrolyte secondary battery according to one aspect of the present disclosure comprises an electrode including a current collector and a mixture layer that is formed on a surface of the current collector and that contains an active material. The current collector includes an electron conductive layer having a gap on the surface in contact with the mixture layer, and an electrolytic solution is present inside the electron conductive layer.
    Type: Application
    Filed: April 12, 2022
    Publication date: June 6, 2024
    Applicant: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Tooru Matsui, Keisuke Asaka, Hirotetsu Suzuki, Motohiro Sakata, Kensuke Nakura
  • Publication number: 20230029282
    Abstract: This separator for nonaqueous electrolyte secondary batteries contains a polymer compound and a solid electrolyte, and has a pore volume of 0.06 cm3/gor less.
    Type: Application
    Filed: December 22, 2020
    Publication date: January 26, 2023
    Applicant: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Kohei Hara, Tooru Matsui, Hirotetsu Suzuki, Motohiro Sakata
  • Publication number: 20220367863
    Abstract: An aluminum foil comprising an aluminum foil substrate that has a porous region, wherein the porous region is formed throughout the entirety of the aluminum foil substrate in the thickness direction thereof.
    Type: Application
    Filed: October 13, 2020
    Publication date: November 17, 2022
    Applicant: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Tooru Matsui, Hiromi Morita, Yoshiki Iwai, Kohei Hara, Hirotetsu Suzuki, Motohiro Sakata
  • Patent number: 11031584
    Abstract: A lithium secondary battery includes: a positive electrode; a negative electrode; a separator disposed between the positive electrode and the negative electrode; and a nonaqueous electrolyte solution filled between the positive electrode and the negative electrode. The negative electrode includes: an electrically conductive layer having a surface; and lithium metal pieces arranged spaced from each other on the surface of the electrically conductive layer. There is no lithium metal on an imaginary line extending from a first end to a second end opposite to the first end of the surface of the electrically conductive layer and traversing a space between the lithium metal pieces.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: June 8, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Tooru Matsui, Junichi Sakamoto, Kazuko Asano, Akira Kano, Kensuke Nakura
  • Patent number: 11018332
    Abstract: A lithium secondary battery includes: a positive electrode; a negative electrode including a negative electrode collector having a surface, on which a lithium metal is deposited during charge; a separator disposed between the positive electrode and the negative electrode; and a nonaqueous electrolyte solution filled between the positive electrode and the negative electrode. The negative electrode collector includes projection portions projecting from the surface toward the separator. There is no projection portion on an imaginary line extending from a first end to a second end opposite to the first end of the surface of the negative electrode collector and traversing a space between the projection portions.
    Type: Grant
    Filed: April 26, 2018
    Date of Patent: May 25, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Tooru Matsui, Junichi Sakamoto, Kazuko Asano, Akira Kano, Kensuke Nakura
  • Patent number: 10840538
    Abstract: A lithium metal secondary battery includes a positive electrode, a negative electrode, a solid electrolyte, and a soft electrolyte. The negative electrode includes a negative electrode current collector having at least one hole, in which lithium metal is deposited in a charged state. The solid electrolyte is disposed on the surface, which face negative electrode current collector, of the positive electrode. The soft electrolyte fills the space between the negative electrode current collector and solid electrolyte and entering into the at least one hole. The solid and soft electrolytes have lithium ion conductivity.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: November 17, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Junichi Sakamoto, Akira Kano, Tooru Matsui, Kazuko Asano, Kiyoshi Kanamura
  • Patent number: 10446492
    Abstract: Disclosed herein is a configuration for ensuring sufficient power supply ability and ESD protection capability for I/O cells in a semiconductor integrated circuit device, without increasing its circuit area. In two I/O cell rows, a pair of I/O cells for supplying a power supply potential or ground potential are connected together via a common power supply interconnect. The I/O cells are arranged so as to overlap with each other in a first direction in which the I/O cells are arranged. The common power supply interconnect extends in a second direction perpendicular to the first direction, and is connected to first pads that are located closest in the first direction to the common power supply interconnect.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: October 15, 2019
    Assignee: SOCIONEXT INC.
    Inventors: Tooru Matsui, Masahiro Yoshimura
  • Patent number: 10438939
    Abstract: Disclosed herein is a configuration for ensuring ESD protection capability for a core power supply of a semiconductor integrated circuit device, without causing an increase in the circuit area. A first pad row in a core region includes a first pad for core power supply. The first pad is connected to a core power supply interconnect, and supplied with a power supply potential or a ground potential. A second pad row provided outwardly from the first pad row includes a second pad for core power supply. The second pad is supplied with the same power supply or ground potential as the first pad for core power supply, and connected to an I/O cell for core power supply.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: October 8, 2019
    Assignee: Socionext Inc.
    Inventor: Tooru Matsui
  • Publication number: 20190115337
    Abstract: Disclosed herein is a configuration for ensuring ESD protection capability for a core power supply of a semiconductor integrated circuit device, without causing an increase in the circuit area. A first pad row in a core region includes a first pad for core power supply. The first pad is connected to a core power supply interconnect, and supplied with a power supply potential or a ground potential. A second pad row provided outwardly from the first pad row includes a second pad for core power supply. The second pad is supplied with the same power supply or ground potential as the first pad for core power supply, and connected to an I/O cell for core power supply.
    Type: Application
    Filed: December 12, 2018
    Publication date: April 18, 2019
    Inventor: Tooru MATSUI
  • Patent number: 10186504
    Abstract: Disclosed herein is a configuration for ensuring ESD protection capability for a core power supply of a semiconductor integrated circuit device, without causing an increase in the circuit area. A first pad row in a core region includes a first pad for core power supply. The first pad is connected to a core power supply interconnect, and supplied with a power supply potential or a ground potential. A second pad row provided outwardly from the first pad row includes a second pad for core power supply. The second pad is supplied with the same power supply or ground potential as the first pad for core power supply, and connected to an I/O cell for core power supply.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: January 22, 2019
    Assignee: SOCIONEXT INC.
    Inventor: Tooru Matsui
  • Publication number: 20180342754
    Abstract: A lithium metal secondary battery includes a positive electrode, a negative electrode, a solid electrolyte, and a soft electrolyte. The negative electrode includes a negative electrode current collector having at least one hole, in which lithium metal is deposited in a charged state. The solid electrolyte is disposed on the surface, which face negative electrode current collector, of the positive electrode. The soft electrolyte fills the space between the negative electrode current collector and solid electrolyte and entering into the at least one hole. The solid and soft electrolytes have lithium ion conductivity.
    Type: Application
    Filed: May 15, 2018
    Publication date: November 29, 2018
    Inventors: JUNICHI SAKAMOTO, AKIRA KANO, TOORU MATSUI, KAZUKO ASANO, KIYOSHI KANAMURA
  • Publication number: 20180337395
    Abstract: A lithium secondary battery includes: a positive electrode; a negative electrode including a negative electrode collector having a surface, on which a lithium metal is deposited during charge; a separator disposed between the positive electrode and the negative electrode; and a nonaqueous electrolyte solution filled between the positive electrode and the negative electrode. The negative electrode collector includes projection portions projecting from the surface toward the separator. There is no projection portion on an imaginary line extending from a first end to a second end opposite to the first end of the surface of the negative electrode collector and traversing a space between the projection portions.
    Type: Application
    Filed: April 26, 2018
    Publication date: November 22, 2018
    Inventors: TOORU MATSUI, JUNICHI SAKAMOTO, KAZUKO ASANO, AKIRA KANO, KENSUKE NAKURA
  • Publication number: 20180337394
    Abstract: A lithium secondary battery includes: a positive electrode; a negative electrode; a separator disposed between the positive electrode and the negative electrode; and a nonaqueous electrolyte solution filled between the positive electrode and the negative electrode. The negative electrode includes: an electrically conductive layer having a surface; and lithium metal pieces arranged spaced from each other on the surface of the electrically conductive layer. There is no lithium metal on an imaginary line extending from a first end to a second end opposite to the first end of the surface of the electrically conductive layer and traversing a space between the lithium metal pieces.
    Type: Application
    Filed: April 26, 2018
    Publication date: November 22, 2018
    Inventors: TOORU MATSUI, JUNICHI SAKAMOTO, KAZUKO ASANO, AKIRA KANO, KENSUKE NAKURA
  • Publication number: 20180269153
    Abstract: Disclosed herein is a configuration for ensuring sufficient power supply ability and ESD protection capability for I/O cells in a semiconductor integrated circuit device, without increasing its circuit area. In two I/O cell rows, a pair of I/O cells for supplying a power supply potential or ground potential are connected together via a common power supply interconnect. The I/O cells are arranged so as to overlap with each other in a first direction in which the I/O cells are arranged. The common power supply interconnect extends in a second direction perpendicular to the first direction, and is connected to first pads that are located closest in the first direction to the common power supply interconnect.
    Type: Application
    Filed: May 17, 2018
    Publication date: September 20, 2018
    Inventors: Tooru MATSUI, Masahiro YOSHIMURA
  • Patent number: 10033049
    Abstract: The present invention provides: a non-aqueous electrolyte for an electrochemical device, having ion conductivity sufficient for practical use and capable of improving energy density; a method for producing the same; and an electrochemical device using the same. The non-aqueous electrolyte for an electrochemical device includes a non-aqueous solvent and an alkaline earth metal chloride. The alkaline earth metal chloride is dissolved in an amount of 0.015 mol or more relative to 1 mol of the non-aqueous solvent. The total content of the non-aqueous solvent and the alkaline earth metal chloride is 70 mass % or more in the non-aqueous electrolyte.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: July 24, 2018
    Assignee: Panasonic Corporation
    Inventors: Tooru Matsui, Zempachi Ogumi, Toshiro Hirai, Akiyoshi Nakata
  • Patent number: 10002832
    Abstract: Disclosed herein is a configuration for ensuring sufficient power supply ability and ESD protection capability for I/O cells in a semiconductor integrated circuit device, without increasing its circuit area. In two I/O cell rows, a pair of I/O cells for supplying a power supply potential or ground potential are connected together via a common power supply interconnect. The I/O cells are arranged so as to overlap with each other in a first direction in which the I/O cells are arranged. The common power supply interconnect extends in a second direction perpendicular to the first direction, and is connected to first pads that are located closest in the first direction to the common power supply interconnect.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: June 19, 2018
    Assignee: Socionext, Inc.
    Inventors: Tooru Matsui, Masahiro Yoshimura
  • Patent number: 9812264
    Abstract: Disclosed is a high-capacity electrochemical energy storage device in which a conversion reaction proceeds as the oxidation-reduction reaction, and the separation (hysteresis) between the electrode potentials for oxidation and reduction is small. The electrochemical energy storage device includes a first electrode including a first active material, a second electrode including a second active material, and a non-aqueous electrolyte interposed between the first and second electrodes. At least one of the first and second active materials is a metal salt having a polyatomic anion and a metal ion, and the metal salt is capable of oxidation-reduction reaction involving reversible release and acceptance of the polyatomic anion.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: November 7, 2017
    Assignee: PANASONIC CORPORATION
    Inventors: Tooru Matsui, Zempachi Ogumi, Toshiro Hirai, Akiyoshi Nakata
  • Publication number: 20170221825
    Abstract: Disclosed herein is a configuration for ensuring sufficient power supply ability and ESD protection capability for I/O cells in a semiconductor integrated circuit device, without increasing its circuit area. In two I/O cell rows, a pair of I/O cells for supplying a power supply potential or ground potential are connected together via a common power supply interconnect. The I/O cells are arranged so as to overlap with each other in a first direction in which the I/O cells are arranged. The common power supply interconnect extends in a second direction perpendicular to the first direction, and is connected to first pads that are located closest in the first direction to the common power supply interconnect.
    Type: Application
    Filed: April 21, 2017
    Publication date: August 3, 2017
    Inventors: Tooru MATSUI, Masahiro YOSHIMURA
  • Publication number: 20170221874
    Abstract: Disclosed herein is a configuration for ensuring ESD protection capability for a core power supply of a semiconductor integrated circuit device, without causing an increase in the circuit area. A first pad row in a core region includes a first pad for core power supply. The first pad is connected to a core power supply interconnect, and supplied with a power supply potential or a ground potential. A second pad row provided outwardly from the first pad row includes a second pad for core power supply. The second pad is supplied with the same power supply or ground potential as the first pad for core power supply, and connected to an I/O cell for core power supply.
    Type: Application
    Filed: April 21, 2017
    Publication date: August 3, 2017
    Inventor: Tooru MATSUI