Patents by Inventor Tooru Ukita

Tooru Ukita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6930744
    Abstract: To make the test probe not directly in contact with the electrode pads for the semiconductor chip mounting, without using an advanced technology for making the pitch of electrode pads narrower, and remove the chip mounting failures such as scratching of electrode pads caused by testing, adherence of impurity particles, electrical corrosion. The electrode pads 13 formed on the distal ends of the external leads 5 for press-connecting the input electrodes 12 of the semiconductor chip 6 are disposed at both sides (shown as L1) of the semiconductor chip 6. The terminal-electrode leads 2 from the electrode pads 3 pass under the semiconductor chip 6 while keeping a pitch of the electrode pads 3. The test electrode pads 4 are disposed in alternate arrangement on the distal ends of terminal-electrode leads 2. The test electrode pads 4 may be disposed in alternate arrangement in three steps or more of multiple steps.
    Type: Grant
    Filed: May 11, 2000
    Date of Patent: August 16, 2005
    Assignee: NEC LCD Technologies, Ltd.
    Inventor: Tooru Ukita
  • Patent number: 6879367
    Abstract: A plurality of connecting terminals 4 orderly arranged in a peripheral portion 2 of a liquid crystal display panel and scan lines derived from a display pixel portion 1 of the liquid crystal display panel are connected by lead wires 3, respectively. Each lead wire 3 includes a meandering portion 3a, an oblique portion extending in nonparallel direction to the scan line and a parallel portion 3c extending in substantially the same direction of the scan line. The meandering portions 3a include a plurality of bent portions, respectively. The number of the bent portions of each meandering portion 3a is regulated correspondingly to a distance between corresponding connecting terminal 4 and wiring of the display pixel portion 1 such that electric resistance of the lead wire 1 becomes within a predetermined range.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: April 12, 2005
    Assignee: NEC LCD Technologies, Ltd.
    Inventor: Tooru Ukita
  • Publication number: 20030086048
    Abstract: A plurality of connecting terminals 4 orderly arranged in a peripheral portion 2 of a liquid crystal display panel and scan lines derived from a display pixel portion 1 of the liquid crystal display panel are connected by lead wires 3, respectively. Each lead wire 3 includes a meandering portion 3a, an oblique portion extending in nonparallel direction to the scan line and a parallel portion 3c extending in substantially the same direction of the scan line. The meandering portions 3a include a plurality of bent portions, respectively. The number of the bent portions of each meandering portion 3a is regulated correspondingly to a distance between corresponding connecting terminal 4 and wiring of the display pixel portion 1 such that electric resistance of the lead wire 1 becomes within a predetermined range.
    Type: Application
    Filed: October 31, 2002
    Publication date: May 8, 2003
    Applicant: NEC Corporation
    Inventor: Tooru Ukita
  • Patent number: 6310668
    Abstract: In a liquid crystal display device, a TFT is formed on a first transparent insulation substrate and includes: a semiconductor layer formed adjacent to a gate insulation film; a drain and a source electrode both formed in opposite ends of the semiconductor layer; and, a gate electrode formed in the gate insulation film so as to be disposed in a partially overlapping relationship with both the drain and the source electrode. The source electrode has a source notch portion which satisfies a predetermined equation to compensate for variations in parasitic capacitance appearing between the source and the gate electrode. The device prevents both its responsivity and its aperture ratio from deteriorating and also prevents its leakage current from increasing. The device is free from any possible restrictions caused by a specific construction of the TFT used in the device.
    Type: Grant
    Filed: June 10, 1999
    Date of Patent: October 30, 2001
    Assignee: NEC Corporation
    Inventor: Tooru Ukita
  • Patent number: 6107668
    Abstract: A first method of forming a thin film transistor substrate having at least an electrode interconnection, wherein a first low resistive metal layer is formed, which extends on the top surface of the substrate by sputtering method. A second low resistive metal layer is formed, which is highly resistant to chemicals and extends on the top of the first low resistive metal layer by sputtering method. A photo-resist film is applied on the second low resistive metal layer for exposure and development thereof to form a photo-resist etching mask. The first and second low resistive metal layers are subjected to an isotropic etching by use of the photo-resist etching mask. A third low resistive metal layer which is highly resistant to chemicals are formed over an entire region of the substrate by sputtering method. The third low resistive metal layer is subjected to a reactive ion etching to leave the third low resistive metal layer on the opposite sides of the first low resistive metal layer.
    Type: Grant
    Filed: May 19, 1998
    Date of Patent: August 22, 2000
    Assignee: NEC Corporation
    Inventor: Tooru Ukita
  • Patent number: 6061112
    Abstract: There is provided a reflection type liquid crystal display including (a) a first substrate having a roughened surface, (b) a second substrate spaced away from the first substrate in opposing relation to the roughened surface of the first substrate, (c) a liquid crystal layer sandwiched between the first and second substrates, (d) a metal film formed on the roughened surface of the first substrate for reflecting lights therefrom, (e) a transparent dielectric film formed on the metal film, the transparent dielectric film having a planarized upper surface, (f) a plurality of transparent pixel electrodes formed on the transparent dielectric film, and (g) a plurality of switching devices formed on the transparent dielectric film, each of the switching devices being electrically connected with each of the transparent pixel electrodes, the transparent pixel electrodes and the switching devices being arranged in a matrix.
    Type: Grant
    Filed: January 12, 1999
    Date of Patent: May 9, 2000
    Assignee: NEC Corporation
    Inventors: Tooru Ukita, Shin Koide
  • Patent number: 5995174
    Abstract: In a liquid crystal display apparatus including a gate electrode formed on an insulating layer a gate insulating layer formed on the gate electrode, and a semiconductor active layer formed on the gate insulating layer, a source electrode and a drain electrode are formed on the semiconductor active layer, and have a double structure including a first conductive layer and a second conductive layer formed on the first conductive layer. Also, a pixel electrode is formed on an insulating layer and is connected to the second conductive layer of the drain electrode via a contact hole perforated in the insulating layer. The pixel electrode is made of the same material as that of the second conductive layer.
    Type: Grant
    Filed: June 26, 1997
    Date of Patent: November 30, 1999
    Assignee: NEC Corporation
    Inventor: Tooru Ukita
  • Patent number: 5940154
    Abstract: There is provided a reflection type liquid crystal display including (a) a first substrate having a roughened surface, (b) a second substrate spaced away from the first substrate in opposing relation to the roughened surface of the first substrate, (c) a liquid crystal layer sandwiched between the first and second substrates, (d) a metal film formed on the roughened surface of the first substrate for reflecting lights therefrom, (e) a transparent dielectric film formed on the metal film, the transparent dielectric film having a planarized upper surface, (f) a plurality of transparent pixel electrodes formed on the transparent dielectric film, and (g) a plurality of switching devices formed on the transparent dielectric film, each of the switching devices being electrically connected with each of the transparent pixel electrodes, the transparent pixel electrodes and the switching devices being arranged in a matrix.
    Type: Grant
    Filed: November 5, 1997
    Date of Patent: August 17, 1999
    Assignee: NEC Corporation
    Inventors: Tooru Ukita, Shin Koide
  • Patent number: 5821159
    Abstract: A first method of forming a thin film transistor substrate having at least an electrode interconnection, wherein a first low resistive metal layer is formed, which extends on the top surface of the substrate by sputtering method. A second low resistive metal layer is formed, which is highly resistant to chemicals and extends on the top of the first low resistive metal layer by sputtering method. A photo-resist film is applied on the second low resistive metal layer for exposure and development thereof to form a photo-resist etching mask. The first and second low resistive metal layers are subjected to an isotropic etching by use of the photo-resist etching mask. A third low resistive metal layer which is highly resistant to chemicals are formed over an entire region of the substrate by sputtering method. The third low resistive metal layer is subjected to a reactive ion etching to leave the third low resistive metal layer on the opposite sides of the first low resistive metal layer.
    Type: Grant
    Filed: December 26, 1996
    Date of Patent: October 13, 1998
    Assignee: NEC Corporation
    Inventor: Tooru Ukita