Abstract: A carbon material for a non-aqueous secondary battery containing a graphite capable of occluding and releasing lithium ions, and having a cumulative pore volume at pore diameters in a range of 0.01 ?m to 1 ?m of 0.08 mL/g or more, a roundness, as determined by flow-type particle image analysis, of 0.88 or greater, and a pore diameter to particle diameter ratio (PD/d50 (%)) of 1.8 or less, the ratio being given by equation (1A): PD/d50 (%)=mode pore diameter (PD) in a pore diameter range of 0.01 ?m to 1 ?m in a pore distribution determined by mercury intrusion/volume-based average particle diameter (d50)×100 is provided.

Abstract: A polishing slurry used in chemical mechanical polishing of a barrier layer and an interlayer dielectric film in a semiconductor integrated circuit includes an abrasive, an oxidizer, an anticorrosive, an acid, a surfactant and an inclusion compound. The polishing slurry has a pH of less than 5. The resulting polishing slurry contains a solid abrasive used in barrier CMP for polishing a barrier layer made of a metallic barrier material, has excellent storage stability, achieves a good polishing rate in various films to be polished such as the barrier layer, and is capable of independently controlling the polishing rate with respect to the various films to be polished while further suppressing agglomeration of the abrasive particles.

Abstract: A polishing slurry used for chemical mechanical polishing of a barrier layer and an interlayer dielectric film in manufacturing a semiconductor integrated circuit includes two colloidal silicas which have association degrees differing from each other by at least 0.5 and primary particle sizes differing from each other by 5.0 nm or less, an anticorrosive, and an oxidizer. The polishing slurry is used in the barrier metal CMP and is capable of achieving a good polishing rate on the interlayer dielectric film while simultaneously reducing scratching which is a defect on the polished surface.

Abstract: A polishing slurry used in chemical mechanical polishing of a barrier layer and an interlayer dielectric film in a semiconductor integrated circuit includes an abrasive, an oxidizer, an anticorrosive, an acid, a surfactant and an inclusion compound. The polishing slurry has a pH of less than 5. The resulting polishing slurry contains a solid abrasive used in barrier CMP for polishing a barrier layer made of a metallic barrier material, has excellent storage stability, achieves a good polishing rate in various films to be polished such as the barrier layer, and is capable of independently controlling the polishing rate with respect to the various films to be polished while further suppressing agglomeration of the abrasive particles.

Abstract: In a solid-state imaging device in which a N-type photoelectric conversion region is formed in a P?-type well region, a light-blocking film and a transparent conductive film are formed on the N-type photoelectric conversion region with a second interlayer insulation film interposed therebetween. By applying a negative voltage to the light-blocking film and the transparent conductive film, a P++-type inversion region is formed in a topmost part of the N-type photoelectric conversion region.

Abstract: A service providing method includes the steps of: a) providing a correspondence between a tag and personal information; and b) providing a service to a person concerning the personal information, for which the correspondence with the tag is provided in the step a), wherein: the step a) comprises the step of registering identification information of an information processing apparatus which the person possesses as the personal information together with identification information of the tag.

Abstract: A first p+-type region on a surface of a photodiode unit is formed over a region from a surface of the photodiode unit through a surface of a signal charge read-out unit until reaching the charge transfer unit. Also, the following structure is adapted: the structure in which a boundary between the first p+-type region and a p++-type region is not on a same plane with a boundary of an n-type impurity region which forms the photodiode unit on a side of the signal charge read-out unit. Further, a second p+-type region is formed between the first p+-type region and the p++-type region on the surface of the photodiode unit. The second p+-type region has an impurity concentration between the impurity concentrations of the first p+-type region and the p++-type region.

Abstract: In a solid-state imaging device including a semiconductor substrate in which photoelectric conversion parts 11a, vertical CCDs 2, and a vertical bus line part 16 are provided, the vertical CCDs 2 are provided with transfer channels 2a, first vertical transfer electrodes 6, second vertical transfer electrodes 9, and shielding films 13. The first transfer electrodes 6 and the second transfer electrodes 9 are arranged so that, in regions where the transfer channels 2a are not formed, the second transfer electrodes 9 are positioned above the first transfer electrodes 6, while in regions where the transfer channels 2a are formed, the first and second transfer electrodes 6 and 9 are arranged so as to be adjoined to each other, and portions of the second transfer electrodes 9 in the regions where the transfer channels 2a are formed do not overlap the first transfer electrodes 9 in the thickness direction of the semiconductor substrate.

Abstract: A p+-type region 5 on a surface of a photodiode unit is formed over a region from a surface of the photodiode unit through a surface of a signal charge read-out unit 9 until reaching the charge transfer unit. Also, the following structure is adapted: the structure in which a boundary between the p+-type region 5 and the p++-type region 4 is not on a same plane with a boundary of an n-type impurity region which forms the photodiode unit on a side of the signal charge read-out unit. Further, a p+-type region 12 is formed between the p+-type region 5 and the p++-type region 4 on the surface of the photodiode unit. The p+-type region 12 has an impurity concentration between the impurity concentrations of the p+-type region 5 and the p++-type region 4.

Abstract: In a solid-state imaging device in which a N-type photoelectric conversion region is formed in a P?-type well region, a light-blocking film and a transparent conductive film are formed on the N-type photoelectric conversion region with a second interlayer insulation film interposed therebetween. By applying a negative voltage to the light-blocking film and the transparent conductive film, a P++-type inversion region is formed in a topmost part of the N-type photoelectric conversion region.

Abstract: A solid-state imaging device of the present invention includes a vertical charge transfer portion and a horizontal charge transfer portion that is connected to at least one end of the vertical charge transfer portion. The vertical charge transfer portion includes a vertical transfer channel region and a plurality of vertical transfer electrodes formed on the vertical transfer channel region. The horizontal charge transfer portion includes a horizontal transfer channel region, a plurality of first horizontal transfer electrodes formed on the horizontal transfer channel region, and a plurality of second horizontal transfer electrodes arranged between the plurality of first horizontal transfer electrodes. A potential below the first horizontal transfer electrode is higher than a potential below the second horizontal transfer electrode that is arranged adjacent to the first horizontal transfer electrode and backward along a transfer direction with respect to the first horizontal transfer electrode.

Abstract: A solid-state imaging device of the present invention includes a vertical charge transfer portion and a horizontal charge transfer portion that is connected to at least one end of the vertical charge transfer portion. The vertical charge transfer portion includes a vertical transfer channel region and a plurality of vertical transfer electrodes formed on the vertical transfer channel region. The horizontal charge transfer portion includes a horizontal transfer channel region, a plurality of first horizontal transfer electrodes formed on the horizontal transfer channel region, and a plurality of second horizontal transfer electrodes arranged between the plurality of first horizontal transfer electrodes. A potential below the first horizontal transfer electrode is higher than a potential below the second horizontal transfer electrode that is arranged adjacent to the first horizontal transfer electrode and backward along a transfer direction with respect to the first horizontal transfer electrode.

Abstract: In a solid-state imaging device in which a N-type photoelectric conversion region is formed in a P−-type well region, a light-blocking film and a transparent conductive film are formed on the N-type photoelectric conversion region with a second interlayer insulation film interposed therebetween. By applying a negative voltage to the light-blocking film and the transparent conductive film, a P++-type inversion region is formed in a topmost part of the N-type photoelectric conversion region.

Abstract: In a solid-state imaging device in which a N-type photoelectric conversion region is formed in a P−-type well region, a light-blocking film and a transparent conductive film are formed on the N-type photoelectric conversion region with a second interlayer insulation film interposed therebetween. By applying a negative voltage to the light-blocking film and the transparent conductive film, a P++-type inversion region is formed in a topmost part of the N-type photoelectric conversion region.

Abstract: This invention comprises a Pd layer formed on an n-type GaAs semiconductor crystals, and a Ge layer being formed on the Pd layer, characterized in that the thickness of the Pd layer is between 300 .ANG. and 1500 .ANG. and the thickness of the Ge layer is between 500 .ANG. and 1500 .ANG..In addition, this invention provides an ohmic electrode forming process for compound semiconductor crystals for forming an ohmic electrode on an n-type GaAs semiconductor crystal, comprising a first layer forming step for forming a palladium (pd) layer on a compound semiconductor crystal; a second layer forming step for forming a germanium layer (Ge) on the Pd layer; and an annealing step for annealing the Pd layer and the Ge layer by a rapid thermal annealing treatment.The Pd layer is formed between 300 .ANG. and 1500 .ANG. in the first layer forming step; the Ge layer is between 500 .ANG. and 1500 .ANG.

Abstract: This invention comprises a Pd layer formed on an n-type GaAs semiconductor crystals, and a Ge layer being formed on the Pd layer, characterized in that the thickness of the Pd layer is between 300 .ANG. and 1500 .ANG. and the thickness of the Ge layer is between 500 .ANG. and 1500 .ANG..And this invention provides an ohmic electrode forming process for compound semiconductor crystals for forming an ohmic electrode on n-type GaAs semiconductor crystals, comprising a first layer forming step for forming a palladium (Pd) layer on a compound semiconductor crystal; a second layer forming step for forming a germanium layer (Ge) on the Pd layer; and a annealing step for annealing the Pd layer and the Ge layer by a rapid thermal annealing treatment.The Pd layer is formed between 300 .ANG. and 1500 .ANG. in the first layer forming step; the Ge layer is between 500 .ANG. and 1500 .ANG.

Abstract: A high-frequency cable connector for relaying coaxial cables led from two different sides to each other comprises a case body having a receptacle for a terminal plug of one of the cables, a holder for holding an inner contactor for contacting therewith the inner conductor of a cable within the case body, a conducting shield plate secured to the bottom of the case body while exposing part of the holder to the exterior, and a cap plate rotatably mounted to the shield plate and holding the other coaxial cable. The connector allows the two coaxial cables to be connected in an extremely simpler manner, the connector itself can be installed along with any other type or same type of wiring devices, and respective components can be assembled in a single direction so as to render efficient its mass production.