Patents by Inventor Tooru Yamaoka

Tooru Yamaoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6348735
    Abstract: The purpose of the present invention is to obtain an electrode wiring structure for semiconductor devices that can suppress the occurrence of Al voids inside aluminum alloy wiring without regard to the orientation of such aluminum alloy wiring. An interlayer insulator film 11, a titanium layer 12, a titanium nitride layer 13 that serves as the barrier layer, an aluminum alloy wiring layer 15 and a protective film 18 are formed on top of the silicon substrate 10 to compose the electrode structure. In this case, a distortion relaxation layer 14, with a film thickness of approximately over 10 nm and which is an intermetallic compound that includes aluminum and titanium in its composition, is formed in between the titanium nitride layer 13 and the aluminum alloy wiring layer 15. Because of this distortion relaxation layer, for every wiring width of 1 &mgr;m, the number of Al voids with widths of over 0.3 &mgr;m is practically reduced to 0.
    Type: Grant
    Filed: January 14, 2000
    Date of Patent: February 19, 2002
    Assignee: Nippondenso Co., Lt.
    Inventors: Tooru Yamaoka, Atsushi Komura, Takeshi Yamauchi, Yoshihiko Isobe, Hiroyuki Yamane
  • Patent number: 6066891
    Abstract: The purpose of the present invention is to obtain an electrode wiring structure for semiconductor devices that can suppress the occurrence of Al voids inside aluminum alloy wiring without regard to the orientation of such aluminum alloy wiring. An interlayer insulator film 11, a titanium layer 12, a titanium nitride layer 13 that serves as the barrier layer, an aluminum alloy wiring layer 15 and a protective film 18 are formed on top of the silicon substrate 10 to compose the electrode structure. In this case, a distortion relaxation layer 14, with a film thickness of approximately over 10 nm and which is an intermetallic compound that includes aluminum and titanium in its composition, is formed in between the titanium nitride layer 13 and the aluminum alloy wiring layer 15. Because of this distortion relaxation layer, for every wiring width of 1 .mu.m, the number of Al voids with widths of over 0.3 .mu.m is practically reduced to 0.
    Type: Grant
    Filed: February 19, 1997
    Date of Patent: May 23, 2000
    Assignee: Nippondenso Co., Ltd
    Inventors: Tooru Yamaoka, Atsushi Komura, Takeshi Yamauchi, Yoshihiko Isobe, Hiroyuki Yamane
  • Patent number: 5592004
    Abstract: A semiconductor device includes a semiconductor element. A silicon nitride film covers the semiconductor element. The silicon nitride film is made of Si.sub.X N.sub.Y H.sub.Z, where X, Y, and Z denote atomic fractions of Si, N, and H respectively. The silicon nitride film relates to an optical absorption edge wavelength shorter than 254 nm. A mean area of regions surrounded by crystal-like grain boundaries at a surface of the silicon nitride film is equal to 4.5.times.10.sup.4 nm.sup.2 or more. The semiconductor element may include a memory element from which information can be erased by exposure to ultraviolet rays.
    Type: Grant
    Filed: September 28, 1995
    Date of Patent: January 7, 1997
    Assignee: Nippondenso Co., Ltd.
    Inventors: Muneo Tamura, Takeshi Yamauchi, Katuhide Niwa, Takeshi Fukazawa, Akira Kuroyanagi, Tooru Yamaoka
  • Patent number: 5018001
    Abstract: An aluminum line including nitrogen formed as a film in a semiconductor integrated circuit is disclosed. Each crystal grain size of the aluminum line is lower than or equal to 0.3 .mu.m to suppress electromigration. A method of forming the aluminum line which can supress electromigration is also disclosed. The amount of an inert gas Q and the amount of a nitrogen gas Q.sub.N are controlled to satisfy "2.ltoreq.(Q.sub.N /Q).times.100.ltoreq.10".
    Type: Grant
    Filed: November 29, 1989
    Date of Patent: May 21, 1991
    Assignee: Nippondenso Co., Ltd.
    Inventors: Kenji Kondo, Kazuo Akamatsu, Takeshi Yamauchi, Tooru Yamaoka, Atsushi Komura