Patents by Inventor Tooru Yanagisawa

Tooru Yanagisawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5898324
    Abstract: For providing a high voltage detector circuit for discriminating whether a voltage supplied to an input terminal (1) is higher or not than a power supply thereof, stably independent of its power supply fluctuation or noises and without problem of gate oxide break because of high voltage; a high voltage detector circuit of the invention comprises: a MOS transistor (P1) with its gate connected to the power supply; a first resistor (R1) connected between a source of the MOS transistor and the input terminal; a second resistor (R2) connected between a drain of the MOS transistor and a ground; and an inverter for outputting inverse logic of a drain voltage of the MOS transistor to an output terminal (OUT).
    Type: Grant
    Filed: March 31, 1997
    Date of Patent: April 27, 1999
    Assignee: NEC Corporation
    Inventor: Tooru Yanagisawa