Abstract: A lateral PNP bipolar transistor includes concentric circular emitter and annular base and dual collector regions. The inner collector region is moderately doped to provide good punch-through and Early voltage performance. The outer collector region is highly doped to provide low collector series resistance. A composite transistor made up of any desired number of individual transistors provides a transistor having a desired current capacity. The transistor annular base cross-section permits very accurate base width control during the manufacturing process.

Abstract: An improved NPN transistor and method of building thereof includes: a P- substrate 50; a N+ buried region 52 provided therein; a N- epitaxial layer 56 deposited onto the N buried region; a P base diffusion region 66 in the N- epi layer; a N+ reach-through region 60 through the N- epi layer to the N+ buried layer to thereby define a collector; a N++ implant or diffusion region 102 provided in the P base diffusion region to thereby define an emitter; and a P++ implant region 74 provided around the N++ emitter implant region which thereby defines the extrinsic base of the transistor, wherein the P++ implant region extends through the P region into the N- epi layer and wherein the P++ implant region extends as close to the N++ emitter implant region as possible without encroaching on the emitter.

Abstract: The method suggests the replacement of all or part of the solid or blanket buried region, typically a subcollector region of a bipolar transistor, by a mesh or stripe shaped subcollector. During subsequent thermal processing involving growth of the epitaxial layer, the stripes will at least partially merge, resulting in a solid subcollector. The method of minimizing autodoping implies only a special design of the subcollector mask. Therefore, there is no longer any need for technological changes either in the process or in the equipment. The method also applies to other buried layers, such as, subemitters, resistors, bottom isolation regions, etc.

Abstract: Disclosed is a method of forming a precision integrated resistor element on a semiconductor wafer whose resistance value accurately corresponds to its nominal design value. The method comprises forming a resistor body in combination with a test resistor structure by conventional ion implantation or diffusion of suitable dopant in selected regions of the wafer. Then, by measuring the resistance(s) and width(s) of the test structure the variation .DELTA..rho..sub.s in sheet resistance and variation .DELTA.W in width due to process and image tolerances, respectively, are determined. Next, using .DELTA..rho..sub.s and .DELTA.W the adjustment in length .DELTA.L necessary to match the resistance of the resistance element with the nominal design value is calculated. Finally, this information (.DELTA.