Abstract: A fault tolerant queue system for selecting storing positions in a memory for performing write operations from an on-line maintained idle list of addresses to free storing positions in the memory and for calculating addresses for collecting data earlier stored in the memory. The storing positions are exposed to a testing procedure. The testing procedure is performed periodically on each storing position in idle cycles during operation of the system, and the result is used to maintain the idle list. The addresses selected for testing are released from system use as controlled by the system.

Abstract: A bit synchronizer for the interpretation of a bit data stream received in a receiver when strobed by an isochronous or plesiochronous clock signal which lies in the receiver time domain is disclosed. This is achieved by alternate activation and deactivation of a first and a second phase aligner respectively, based on monitoring a delay controlled voltage of the active phase aligner. These phase aligners each utilizes differential delay lines which are comprised of differential delay elements, which in turn are comprised of pairs of inverting devices, where both devices of each pair have a controllable delay for positive edges and a pulse form restoring function for negative edges, alternatively a controllable delay for negative edges and a pulse form restoring function for positive edges.