Abstract: A power module for a computer system includes an internal source of stored energy and a group of interface ports, including a management port and non-management ports. The management port provides a control interface to control the power module. The non-management ports each lack the control interface of the management port, and each provide a signal indicating that the power module has a sufficient amount of the stored energy to power a defined operation by external devices coupled to and drawing power from said non-management ports. The management port will typically provide a similar signal to the coupled management device. The signal may be implemented as a high or low voltage level on a serial interface cable pin.

Abstract: A method of restoring an encrypted memory image in a system comprising volatile and non-volatile memory initiates a RESTORE of the image from the non-volatile memory to the volatile memory during a BIOS phase of a boot process for the system. If, during an operating system phase, it is determined that the RESTORE failed due to a password error, a password is written to the non-volatile memory and the BIOS phase of the boot process is reinitiated.

Abstract: A method of restoring an encrypted memory image in a system comprising volatile and non-volatile memory initiates a RESTORE of the image from the non-volatile memory to the volatile memory during a BIOS phase of a boot process for the system. If, during an operating system phase, it is determined that the RESTORE failed due to a password error, a password is written to the non-volatile memory and the BIOS phase of the boot process is reinitiated.

Abstract: A sequential delay mechanism is provided for a memory subsystem of a host system. A first independent SAVE region of NVDIMMs of the memory subsystem is configured to start a memory SAVE immediately upon receiving a SAVE signal from the host system, and other independent SAVE regions of the NVDIMMs are configured to implement the delay mechanism. A memory SAVE to the NVDIMMs is activated immediately in the first independent SAVE region when the SAVE signal is received, and the other independent SAVE regions sequentially delay their activation of the memory SAVE.

Abstract: A power module for a computer system includes an internal source of stored energy and a group of interface ports, including a management port and non-management ports. The management port provides a control interface to control the power module. The non-management ports each lack the control interface of the management port, and each provide a signal indicating that the power module has a sufficient amount of the stored energy to power a defined operation by external devices coupled to and drawing power from said non-management ports. The management port will typically provide a similar signal to the coupled management device. The signal may be implemented as a high or low voltage level on a serial interface cable pin.

Abstract: A process of interacting with a memory module to restore data backed up from volatile memory to nonvolatile memory of the memory module involves a host system configuring the volatile memory of the module to interoperate with a host memory controller via a DIMM memory interface to the module; the host configuring a controller of the module to copy data from the nonvolatile memory to a peripheral I/O bus, the configuration of the controller of the module carried out via the peripheral I/O bus; a host I/O controller receiving the data copied to the peripheral I/O bus and communicating the received data to a host memory controller; and the host memory controller copying the received data to the volatile memory via the DIMM memory interface, thus completing a restore of the data from nonvolatile memory to the volatile memory.

Abstract: A memory module interfaces with a host system as a Dual Inline Memory Module (DIMM). The memory module includes a volatile memory and a nonvolatile memory, and provides a DIMM module interface to the volatile memory. A peripheral I/O bus interfaces to the nonvolatile memory, the peripheral I/O bus interface also interfaces to control logic of the memory module to initiate data backup from the volatile to the nonvolatile memory.