Abstract: Systems and methods for testing the thermal conditioning of an integrated circuit (IC) are disclosed. In one aspect, a device is used to apply heat to a chip, and more particularly to a memory element, while providing thermal isolation to a motherboard with which circuits in the chip may be operating. Testing sensors may monitor operation of the circuits in the chip while the heat is applied to the chip. Having a device that is easily coupled to the chip under test, readily applies heat without damaging other components on a motherboard and allows testing of the chip under test will save time and provide better test results so that chips may be certified for operation at such elevated temperatures and/or provide a better product to customers.

Abstract: An energy source for a memory device is disclosed. In particular, a memory device such as an insertable memory card may include a detachable portion that has an energy source positioned thereon. The junction between the primary portion and the detachable portion includes sufficient conductors to convey power from the energy source as well as any needed control signals. In an exemplary aspect, the detachable portion is positioned relative to the primary portion such that the detachable portion may be readily removed while the memory device is installed in a computing device. By providing a detachable energy source, the energy source may readily be replaced in the event of failure without having to replace the entirety of the memory device. Such flexibility may save time, money, and otherwise simplify design requirements.

Abstract: Memory packages are employed in computer processing systems to house memory chips that store data for a processing circuit. The memory chips consume power each time they are accessed, which may be thousands of times per second, which generates heat that needs to be dissipated to avoid high temperatures that may damage memory circuits in the memory chips. The memory packages may include at least one memory chip disposed on a substrate. The memory packages may also include an active cooling device disposed between the memory chips and a package surface to actively conduct heat from the memory chips to the package surface, where it may be dissipated. The active cooling device May be on an opposite side of the memory chips from the substrate or may be disposed in a cavity in the substrate.

Abstract: Systems and methods for memory snapshots are disclosed. In particular, a memory device may include a volatile section and a backup persistent storage section. A snapshot manager circuit is positioned between a host control circuit or central processors. This snapshot manager circuit acts as a memory virtualization layer within the memory device and may use a redirect on write type command to put a snapshot of actively changed memory to a reserved memory area in the volatile section. A background function may copy the snapshots to the persistent storage section. Because the snapshot manager circuit is in the hardware memory access layers of the memory device, operation of the application is not interrupted or paused to access the specific memory sections. Further, snapshots are more readily available in the memory used by the host control circuit.

Abstract: Memory modules comprise memory chips coupled to a surface of one or more substrates. The memory chips contain large numbers of storage cells that consume power during normal operation, generating heat in the memory chips and causing temperatures to increase. As the temperatures increase, leakage currents can increase in the memory chips, and performance of the memory chips can decrease. A memory module includes memory chips disposed on a substrate and an active cooling device disposed on the substrate to increase the rate at which heat is dissipated to reduce or maintain temperatures and thereby save power and improve performance. In some examples, the active cooling device is disposed on a side of a memory chip opposite to the card in the memory module to improve cooling of the memory chips. In some examples, the active cooling device is a thermoelectric device.

Abstract: Systems and methods for memory snapshots are disclosed. In particular, a memory device may include a volatile section and a backup persistent storage section. A snapshot manager circuit is positioned between a host control circuit or central processors. This snapshot manager circuit acts as a memory virtualization layer within the memory device and may use a redirect on write type command to put a snapshot of actively changed memory to a reserved memory area in the volatile section. A background function may copy the snapshots to the persistent storage section. Because the snapshot manager circuit is in the hardware memory access layers of the memory device, operation of the application is not interrupted or paused to access the specific memory sections. Further, snapshots are more readily available in the memory used by the host control circuit.

Abstract: Systems and methods for balancing memory speeds are disclosed. In particular, at start up, a host to memory bus speed is determined and compared to a default internal memory device bus speed. A memory device control circuit may then determine if an internal bus should be overclocked or slowed down to match the host to memory bus speed. The selection may then be stored in a register and made available to a host memory controller (e.g., through polling or the like). Selection of an internal speed may also be based on other factors such as power savings or the like. In either event, having the flexibility to set the internal speed based on one or more such criteria may result in improved efficiency.

Abstract: Systems and methods for enabling serial attached Non-Volatile (NV) memory are provided. In some embodiments, a method of operation of a computing system includes: in an NV Random Access Memory module (NVRAM) having a non-volatile device, a volatile memory device with data, a NV Controller unit (NVC), and a serial host interface, the method includes: receiving a request for data on the serial host interface and providing the requested data, from the volatile memory device, on the serial host interface. The method also includes: detecting a disruptive volatile memory event; copying the data of the volatile memory device to the NV device through the serial host interface based on the disruptive volatile memory event; and restoring the data of the volatile memory device from the NV device through the serial host interface. In this way, Dynamic Random-Access Memory (DRAM) level endurance and speed/latency can be provided while making it NV.

Abstract: A comb filter system that utilizes host memory is disclosed. The comb filter system that utilizes host memory may include a comb filter. The comb filter system that utilizes host memory may include an allocated host memory. The comb filter system that utilizes host memory may include an interface in signal communication with the comb filter and allocated host memory.

Abstract: A comb filter system that utilizes host memory (“CFSHM”) is disclosed. The CFSHM may include a comb filter, an allocated host memory, and an interface in signal communication with the comb filter and allocated host memory.