Abstract: A lock detecting circuit of a phase locked loop, comprising a phase comparator for receiving a reference frequency signal and a signal being compared with the reference frequency signal, a charging/discharging circuit which is charge/discharge controlled responsive to the output of the phase comparator and either of the above described two signals, and a delay flip-flop responsive to the output of the charging/discharging circuit and in synchronism with the signal applied to the charging/discharging circuit for assuming one storing state for providing an output representative of the phase difference between the above described two signals.

Abstract: A flip-flop having a reset preferential function, comprising a set input terminal, a reset input terminal, a clock signal source operatively coupled through a field effect transistor to the set input terminal, a capacitance formed at the gate electrode of the field effect transistor, a charge control transistor controllable responsive to the clock signal for precharging the capacitance prior to the clock signal, a discharge control transistor controllable responsive to the reset signal for discharging the capacitance, whereby the capacitance is precharged prior to the clock signal and is discharged responsive to the reset signal, the field effect transistor being rendered conductive as a function of the electric charge of the capacitance, the clock signal source being operatively coupled to the set input terminal as a function of the conduction state of the field effect transistor, whereby the flip-flop is set responsive to the leading edge of the clock signal and is reset responsive to the reset signal in pr