Abstract: In an array-type processor in which a multiplicity of processor elements, which each execute data processing in accordance with instruction codes in which data are individually set, are arranged in rows and columns, and in which state control units cause successive transitions of the operating states of this multiplicity of processor elements for each operating cycle by means of contexts that are make up by instruction codes, a plurality of element areas are respectively connected to an equal number of state control units, and state control units that correspond to a prescribed number of operating states that are set to one context temporarily halt the operation of element areas to which the state control unit is connected during operating cycle in which operating states do not occur.

Abstract: A multiplicity of processor elements that are arranged in rows and columns individually execute data processing in accordance with instruction codes that are individually set as data and supply event data as output. A state control unit is composed of a plurality of units that successively switch the instruction codes of the multiplicity of processor elements in accordance with a computer program and the event data, these state control units communicating with each other to realize linked operation as necessary. An event distributing means distributes event data to this plurality of state control units that intercommunicate to realize linked operation, whereby the plurality of state control units can realize linked operation to control a large-scale state transition.

Abstract: A multiplicity of processor elements, which both individually execute data processing in accordance with instruction codes that have been set as data and for which mutual connection relations are switch-controlled, are arranged in matrix form, and the instruction codes of this multiplicity of processor elements are successively switched by a state control unit. The state control units are composed of a plurality of units that intercommunicate to realize linked operation, and the multiplicity of processor elements is divided into a number of element areas that corresponds to the number of state control units. The plurality of state control units are arranged for each of the plurality of element areas and are connected to the processor elements, whereby the plurality of state control units can individually control a plurality of small-scale state transitions, or the plurality of state control units can cooperate to control a single large-scale state transition.

Abstract: A multiplicity of processor elements, which individually execute data processing in accordance with instruction codes that are individually set and for which the connection relation between processor elements is switch-controlled, are arranged in a matrix; and the instruction codes of the multiplicity of processor elements are successively switched by a state control unit. The state control unit is composed of a plurality of units that intercommunicate to realize linked operation, the multiplicity of processor elements is divided into a plurality of element groups, and the plurality of state control units and the plurality of element groups are individually connected, whereby a plurality of small-scale state transitions can be individually controlled by the state control units, or a single large-scale state transition can be controlled through the cooperation of the plurality of state control units.

Abstract: At least one of a plurality of data processors of a data processing system is an array-type processor, and the data processing of this array-type processor and the other data processors is effectively linked. The array-type processor and other data processors, which process the process data in accordance with event data and issue event data in accordance with this data processing, communicate to each other at least a portion of the process data and at least a portion of the event data and thus link the data processing.

Abstract: An object code for sequentially switching contexts of processing circuits arrayed in a matrix in a parallel operation apparatus is generated from a general source code descriptive of operation of the parallel operation apparatus. A DFG is generated from the source code descriptive of operation of the parallel operation apparatus according to limiting conditions, registered in advance, representing a physical structure, etc. of the parallel operation apparatus, and scheduled in a CDFG. An RTL description is generated from the CDFG, converting a finite-state machine into an object code and converting a data path into a net list. An object code of the processing circuits is generated in each context from the net list.