Abstract: A semiconductor device has a semiconductor chip which is usable as any one of 4-bit, 8-bit, and 16-bit structure devices, and a package for packaging the semiconductor chip. The semiconductor chip has first and second DQ pad groups of DQ system pads for said 16-bit structure device. The first DQ pad group is arranged in a first area at a vicinity of a middle part of a surface of the semiconductor chip while the second DQ pad group is arranged in a second area at an outer side of the first area on the surface. An additional pad necessary as one of DQ system pads for the 8-bit structure device except for pads included in the second DQ pad group is formed in the second area.

Abstract: A conduction member is used to connect in-chip equipotential pads 20 that have the same potential in a semiconductor device through PKG ball 10 arranged on the semiconductor device.

Abstract: A semiconductor device has a semiconductor chip which is usable as any one of 4-bit, 8-bit, and 16-bit structure devices, and a package for packaging the semiconductor chip. The semiconductor chip has first and second DQ pad groups of DQ system pads for said 16-bit structure device. The first DQ pad group is arranged in a first area at a vicinity of a middle part of a surface of the semiconductor chip while the second DQ pad group is arranged in a second area at an outer side of the first area on the surface. An additional pad necessary as one of DQ system pads for the 8-bit structure device except for pads included in the second DQ pad group is formed in the second area.

Abstract: DC voltage VREF produced in an LSI and having a value between power supply voltage VDD and the ground potential is applied to the gate electrode of pMOS transistor QP1 which forms a function determination circuit. Since the gate voltage of a transistor QP1 is lower than that in a conventional function determination circuit, current through the transistor QP1 is reduced. Hence, the gate length of the transistor QP1 can be reduced. When a second pMOS transistor is connected in parallel to the transistor QP1 so that the transistor has a function for supplying charge to junction A when power is fed to the LSI, the area of the transistor QP1 can be further reduced. When a voltage produced for a purpose other than for the function determination circuit such as a step-down power supply of the LSI is used as DC voltage, the area of the transistor can be reduced.

Abstract: DC voltage VREF produced in an LSI and having a value between power supply voltage VDD and the ground potential is applied to the gate electrode of pMOS transistor QP1 which forms a function determination circuit. Since the gate voltage of a transistor QP1 is lower than that in a conventional function determination circuit, current through the transistor QP1 is reduced. Hence, the gate length of the transistor QP1 can be reduced. When a second pMOS transistor is connected in parallel to the transistor QP1 so that the transistor has a function for supplying charge to junction A when power is fed to the LSI, the area of the transistor QP1 can be further reduced. When a voltage produced for a purpose other than for the function determination circuit such as a step-down power supply of the LSI is used as DC voltage, the area of the transistor can be reduced.

Abstract: A semiconductor memory device according to the invention comprises a first memory cell region, a second memory cell region, and a sense-amplifier row region disposed between the first and second memory cell regions, wherein the sense-amplifier row region has therein a plurality of transistor rows constituting a plurality of sense-amplifiers, at least one power-supply side sense-amplifier driver transistor disposed on the side f the first memory cell region of the plurality of transistor rows, and at least one ground side sense-amplifier driver transistor disposed on the side of the second memory cell region of the plurality of transistor rows.

Abstract: A test circuit for a DRAM is disclosed to preform a test operation in a page mode. The test circuit includes a compare control block 7A having a compare determination signal generator circuit 71 which generates a compare determination signal .PHI.1 in response to a change from an active low level to an inactive high level of column address strobe or CAS signal during an active low level of a row address strobe or RAS signal.

Abstract: A substrate potential detection circuit includes a substrate potential detection unit including a first transistor having a gate and a source connected respectively to a ground line and a reference voltage line, a second transistor having a gate receiving a substrate potential and a drain connected to the ground, and a third transistor having a source connected to the drain of the first transistor and a gate and a drain connected in common to the source of the second transistor to form a detection output node; and a buffer circuit having a drive transistor and a current source, a gate and a source of the drive transistor being connected respectively to the detection output node and the reference voltage line and outputting a substrate detection voltage.

Abstract: Disclosed therein is a dynamic memory device having an internal power source circuit generating an internal power voltage which is smaller than an external power voltage applied to the device and supplied to an internal memory circuit as an operating voltage. The internal power source circuit includes a differential amplifier for stabilizing the internal power voltage in response to a reference voltage, and a current flowing through the differential amplifier is controlled to a first value during a standby mode, a second value larger than the first value during a data sensing operation and restoring (refreshing) operation of an active mode, and a third value larger than the first value but smaller than the second value during the other operation of the active mode.

Abstract: A semiconductor memory device has an addressable data storage powered with an internal step-down power voltage for storing data bits, a signal buffer circuit powered with a non-step-down power voltage for producing an internal output enable signal, an output data buffer circuit powered with the non-step-down power voltage and enabled with the internal output enable signal for producing an output data signal from a read-out data bit and a delay circuit connected between the signal buffer circuit and the output data buffer circuit for introducing delay into propagation of the internal output enable signal, and the delay circuit is implemented by a plurality of complementary inverters connected in cascade, wherein the p-channel enhancement type field effect transistors of the complementary inverters have source nodes connected with an internal step-down power voltage line and channel regions biased with the non-step-down power voltage so that the delay is proportional to the external power voltage.