Patents by Inventor Toru Fujioka
Toru Fujioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8426941Abstract: A technique capable of promoting miniaturization of an RF power module used in a mobile phone etc. is provided. A directional coupler is formed inside a semiconductor chip in which an amplification part of the RF power module is formed. A sub-line of the directional coupler is formed in the same layer as a drain wire coupled to the drain region of an LDMOSFET, which will serve as the amplification part of the semiconductor chip. Due to this, the predetermined drain wire is used as a main line and the directional coupler is configured by a sub-line arranged in parallel to the main line via an insulating film, together with the main line.Type: GrantFiled: November 1, 2012Date of Patent: April 23, 2013Assignee: Renesas Electronics CorporationInventors: Satoshi Sakurai, Satoshi Goto, Toru Fujioka
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Publication number: 20130056730Abstract: A technique capable of promoting miniaturization of an RF power module used in a mobile phone etc. is provided. A directional coupler is formed inside a semiconductor chip in which an amplification part of the RF power module is formed. A sub-line of the directional coupler is formed in the same layer as a drain wire coupled to the drain region of an LDMOSFET, which will serve as the amplification part of the semiconductor chip. Due to this, the predetermined drain wire is used as a main line and the directional coupler is configured by a sub-line arranged in parallel to the main line via an insulating film, together with the main line.Type: ApplicationFiled: November 1, 2012Publication date: March 7, 2013Inventors: Satoshi SAKURAI, Satoshi GOTO, Toru FUJIOKA
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Patent number: 8334580Abstract: A technique capable of promoting miniaturization of an RF power module used in a mobile phone etc. is provided. A directional coupler is formed inside a semiconductor chip in which an amplification part of the RF power module is formed. A sub-line of the directional coupler is formed in the same layer as a drain wire coupled to the drain region of an LDMOSFET, which will serve as the amplification part of the semiconductor chip. Due to this, the predetermined drain wire is used as a main line and the directional coupler is configured by a sub-line arranged in parallel to the main line via an insulating film, together with the main line.Type: GrantFiled: December 26, 2007Date of Patent: December 18, 2012Assignee: Renesas Electronics CorporationInventors: Satoshi Sakurai, Satoshi Goto, Toru Fujioka
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Patent number: 7868699Abstract: The present invention is to provide a technique which optimizes a gate resistor of a bias circuit to thereby make it possible to greatly improve a distortion characteristic of a power amplifier. A bias circuit used as for biasing the gate of a final-stage power transistor is included in a power amplifier provided in a communication mobile system. In the bias circuit, an inductance and a resistor are series-connected between a power supply voltage and the gate of the power transistor. The resistance value of the resistor is set to approximately the same order as an input impedance of the power transistor. When the input impedance of the power transistor is about 10? or so, for example, the resistor is set to about a few ? to about 100?. Thus, the gain of the power transistor at a low-frequency band can greatly be suppressed.Type: GrantFiled: July 25, 2008Date of Patent: January 11, 2011Assignee: Renesas Electronics CorporationInventors: Hideyuki Ono, Toru Fujioka, Masahito Numanami
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Publication number: 20100301947Abstract: The RF power amplifier includes first and second amplifiers Q1 and Q2 as final-stage amplification power devices connected in parallel between an input terminal RF_In and an output terminal RF_Out. The amplifiers Q1 and Q2 are formed on one semiconductor chip. The first bias voltage Vg1 of the amplifier Q1 is set to be higher than the second bias voltage Vg2 of the amplifier Q2 so that the amplifier Q1 is operational between Class B and AB, and Q2 is operational in Class C. The first effective device size Wgq1 of the amplifier Q1 is intentionally set to be smaller than the second effective device size Wgq2 of the amplifier Q2 beyond a range of a manufacturing error of the semiconductor chip. An RF power amplifier that exhibits a high power-added efficiency characteristic regardless of whether the output power is High or Low can be materialized.Type: ApplicationFiled: June 14, 2010Publication date: December 2, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Toru Fujioka, Toshihiko Shimizu, Masami Ohnishi, Hidetoshi Matsumoto, Satoshi Tanaka
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Patent number: 7756494Abstract: The RF power amplifier includes first and second amplifiers Q1 and Q2 as final-stage amplification power devices connected in parallel between an input terminal RF_In and an output terminal RF_Out. The amplifiers Q1 and Q2 are formed on one semiconductor chip. The first bias voltage Vg1 of the amplifier Q1 is set to be higher than the second bias voltage Vg2 of the amplifier Q2 so that the amplifier Q1 is operational between Class B and AB, and Q2 is operational in Class C. The first effective device size Wgq1 of the amplifier Q1 is intentionally set to be smaller than the second effective device size Wgq2 of the amplifier Q2 beyond a range of a manufacturing error of the semiconductor chip. An RF power amplifier that exhibits a high power-added efficiency characteristic regardless of whether the output power is High or Low can be materialized.Type: GrantFiled: June 18, 2007Date of Patent: July 13, 2010Assignee: Renesas Technology Corp.Inventors: Toru Fujioka, Toshihiko Shimizu, Masami Ohnishi, Hidetoshi Matsumoto, Satoshi Tanaka
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Patent number: 7735219Abstract: A method for machining a board includes forming a backup board, supporting the board by the backup board and machining the board while the board is supported by the backup board. The backup board has a fibrous layer and a surface layer formed on one side of the fibrous layer, the surface layer being in contact with the board during said supporting machining the board. The backup board is formed by: forming an impregnated fibrous mat by impregnating a thermosetting adhesive into a fibrous mat of the kenaf fibers, the kenaf fibers; forming the fibrous layer having a density of about 600-900 kg/m3 by curing the impregnated fibrous mat; forming a resin paper by impregnating a thermosetting resin into a paper; and forming the surface layer on said one side of the fibrous layer by curing the resin paper.Type: GrantFiled: April 19, 2007Date of Patent: June 15, 2010Assignee: Panasonic CorporationInventors: Kazunori Umeoka, Toru Fujioka, Hideyuki Andou, Yuzo Okudaira
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Publication number: 20080287090Abstract: The present invention is to provide a technique which optimizes a gate resistor of a bias circuit to thereby make it possible to greatly improve a distortion characteristic of a power amplifier. A bias circuit used as for biasing the gate of a final-stage power transistor is included in a power amplifier provided in a communication mobile system. In the bias circuit, an inductance and a resistor are series-connected between a power supply voltage and the gate of the power transistor. The resistance value of the resistor is set to approximately the same order as an input impedance of the power transistor. When the input impedance of the power transistor is about 10? or so, for example, the resistor is set to about a few ? to about 100?. Thus, the gain of the power transistor at a low-frequency band can greatly be suppressed.Type: ApplicationFiled: July 25, 2008Publication date: November 20, 2008Inventors: Hideyuki Ono, Toru Fujioka, Masahito Numanami
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Publication number: 20080237736Abstract: A technique capable of promoting miniaturization of an RF power module used in a mobile phone etc. is provided. A directional coupler is formed inside a semiconductor chip in which an amplification part of the RF power module is formed. A sub-line of the directional coupler is formed in the same layer as a drain wire coupled to the drain region of an LDMOSFET, which will serve as the amplification part of the semiconductor chip. Due to this, the predetermined drain wire is used as a main line and the directional coupler is configured by a sub-line arranged in parallel to the main line via an insulating film, together with the main line.Type: ApplicationFiled: December 26, 2007Publication date: October 2, 2008Inventors: Satoshi SAKURAI, Satoshi Goto, Toru FUJIOKA
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Patent number: 7411457Abstract: The present invention is to provide a technique which optimizes a gate resistor of a bias circuit to thereby make it possible to greatly improve a distortion characteristic of a power amplifier. A bias circuit used as for biasing the gate of a final-stage power transistor is included in a power amplifier provided in a communication mobile system. In the bias circuit, an inductance and a resistor are series-connected between a power supply voltage and the gate of the power transistor. The resistance value of the resistor is set to approximately the same order as an input impedance of the power transistor. When the input impedance of the power transistor is about 10? or so, for example, the resistor is set to about a few ? to about 100?. Thus, the gain of the power transistor at a low-frequency band can greatly be suppressed.Type: GrantFiled: May 11, 2006Date of Patent: August 12, 2008Assignee: Renesas Technology Corp.Inventors: Hideyuki Ono, Toru Fujioka, Masahito Numanami
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Publication number: 20070298736Abstract: The RF power amplifier includes first and second amplifiers Q1 and Q2 as final-stage amplification power devices connected in parallel between an input terminal RF_In and an output terminal RF_Out. The amplifiers Q1 and Q2 are formed on one semiconductor chip. The first bias voltage Vg1 of the amplifier Q1 is set to be higher than the second bias voltage Vg2 of the amplifier Q2 so that the amplifier Q1 is operational between Class B and AB, and Q2 is operational in Class C. The first effective device size Wgq1 of the amplifier Q1 is intentionally set to be smaller than the second effective device size Wgq2 of the amplifier Q2 beyond a range of a manufacturing error of the semiconductor chip. An RF power amplifier that exhibits a high power-added efficiency characteristic regardless of whether the output power is High or Low can be materialized.Type: ApplicationFiled: June 18, 2007Publication date: December 27, 2007Inventors: Toru FUJIOKA, Toshihiko Shimizu, Masami Ohnishi, Hidetoshi Matsumoto, Satoshi Tanaka
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Publication number: 20070193680Abstract: A backup board for use in a machining process includes a fibrous layer, at least one side of the fibrous layer being provided with a surface layer adhered and laminated thereon, wherein the surface layer is made of a cured paper impregnated with a thermosetting resin. The fibrous layer has a density of about 600˜900 kg/m3 and includes kenaf fibers adhered together by impregnating a thermosetting adhesive into a fibrous mat of the kenaf fibers, the kenaf fibers having an average length of about 10˜200 mm and an average diameter of about 10˜300 ?m.Type: ApplicationFiled: April 19, 2007Publication date: August 23, 2007Applicant: Matsushita Electric Works, Ltd.Inventors: Kazunori Umeoka, Toru Fujioka, Hideuki Andou, Yuzo Okudaira
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Publication number: 20060255861Abstract: The present invention is to provide a technique which optimizes a gate resistor of a bias circuit to thereby make it possible to greatly improve a distortion characteristic of a power amplifier. A bias circuit used as for biasing the gate of a final-stage power transistor is included in a power amplifier provided in a communication mobile system. In the bias circuit, an inductance and a resistor are series-connected between a power supply voltage and the gate of the power transistor. The resistance value of the resistor is set to approximately the same order as an input impedance of the power transistor. When the input impedance of the power transistor is about 10 ? or so, for example, the resistor is set to about a few ? to about 100 ?. Thus, the gain of the power transistor at a low-frequency band can greatly be suppressed.Type: ApplicationFiled: May 11, 2006Publication date: November 16, 2006Inventors: Hideyuki Ono, Toru Fujioka, Masahito Numanami
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Publication number: 20050176328Abstract: A backup board for use in a machining process includes a fibrous layer, at least one side of the fibrous layer being provided with a surface layer adhered and laminated thereon, wherein the surface layer is made of a cured paper impregnated with a thermosetting resin. The fibrous layer has a density of about 600˜900 kg/m3 and includes kenaf fibers adhered together by impregnating a thermosetting adhesive into a fibrous mat of the kenaf fibers, the kenaf fibers having an average length of about 10˜200 mm and an average diameter of about 10˜300 ?m.Type: ApplicationFiled: October 8, 2004Publication date: August 11, 2005Applicant: Matsushita Electric Works, Ltd.Inventors: Kazunori Umeoka, Toru Fujioka, Hideyuki Andou, Yuzo Okudaira
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Patent number: 6865399Abstract: In a mobile telephone apparatus corresponding to dual-band provided with an RF power module to operate in two kinds of different frequencies, a common harmonics control circuit is provided to the output circuit of such RF power module to realize higher efficiency in view of controlling respective harmonics power for both band frequencies. Moreover, a means for selectively setting the bias is also provided so that the maximum efficiency can be attained depending on the output power required with respective communication systems with the bias control signal output from the CPU of the control unit interlocking with selection of frequency of the mobile telephone apparatus body.Type: GrantFiled: February 5, 2002Date of Patent: March 8, 2005Assignee: Renesas Technology Corp.Inventors: Toru Fujioka, Isao Yoshida, Mineo Katsueda, Masatoshi Morikawa, Yoshikuni Matsunaga, Kenji Sekine, Osamu Kagaya
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Patent number: 6825548Abstract: It is to be made possible to eliminate unevenness of the inductances of bonding wires and to reduce the size of semiconductor devices. Over the surface of a semiconductor device in whose MISFET formation area a MISFET comprising a plurality of unit MISFETs connected in parallel, gate electrode pads electrically connected to the gate electrode of the MISFET and drain electrode pads electrically connected to the drain electrode of the same are arranged in a row each. The intervals of the gate electrode pads become gradually shorter from the end areas towards the central area of the electrode array of the gate electrode pads. The intervals of the drain electrode pads also become gradually shorter from the end areas towards the central area of the electrode array of the drain electrode pads.Type: GrantFiled: June 6, 2003Date of Patent: November 30, 2004Assignee: Renesas Technology Corp.Inventors: Toru Fujioka, Isao Yoshida, Toshihiko Shimizu
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Publication number: 20040145034Abstract: A semiconductor device for amplification with enhanced performance is provided for use at a base station. The semiconductor device has a semiconductor chip for amplification and a transmission line substrate in the package of an amplifier used at a base station for mobile communication equipment such as a mobile phone. Stubs formed in the empty region of the transmission line substrate are connected to an output of the semiconductor chip for amplification by using bonding wires. The stubs and the bonding wires have been designed to form a resonant circuit resonating at a frequency double the fundamental frequency of an output signal from the semiconductor chip for amplification. This suppresses a doubled-frequency-wave signal of the signal outputted from the semiconductor chip for amplification and achieves an improvement in the transmission efficiency of the amplifier and a reduction in transmission distortion.Type: ApplicationFiled: January 9, 2004Publication date: July 29, 2004Inventors: Toru Fujioka, Toshihiko Shimizu, Isao Yoshida, Mamoru Ito, Koji Odaira, Tetsuya Iida
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Publication number: 20040000676Abstract: It is to be made possible to eliminate unevenness of the inductances of bonding wires and to reduce the size of semiconductor devices. Over the surface of a semiconductor device in whose MISFET formation area a MISFET comprising a plurality of unit MISFETs connected in parallel, gate electrode pads electrically connected to the gate electrode of the MISFET and drain electrode pads electrically connected to the drain electrode of the same are arranged in a row each. The intervals of the gate electrode pads become gradually shorter from the end areas towards the central area of the electrode array of the gate electrode pads. The intervals of the drain electrode pads also become gradually shorter from the end areas towards the central area of the electrode array of the drain electrode pads.Type: ApplicationFiled: June 6, 2003Publication date: January 1, 2004Inventors: Toru Fujioka, Isao Yoshida, Toshihiko Shimizu
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Patent number: 6535069Abstract: A radio frequency power amplifier module for a dual-band type mobile communication apparatus that can transmit and receive a first frequency f1 and second frequency f2 (f2=2×f1). It includes a drive stage amplifier having the gain peaks at f1 and f2 with a matching circuit and a radio frequency power output circuit including a radio frequency power output transistor. The output circuit has a transmission line connected to the drain end of the output transistor, a parallel resonance circuit connected in series to the transmission line to resonate at harmonics of a frequency twice the frequency f2, a series resonance circuit provided between one end of the resonance circuit and the ground to resonate at harmonics of a frequency twice the frequency f2 and an output matching circuit provided in series to the other end of the parallel resonance circuit for matching with f1 and f2.Type: GrantFiled: February 28, 2002Date of Patent: March 18, 2003Assignee: Hitachi, Ltd.Inventors: Toru Fujioka, Isao Yoshida, Mineo Katsueda, Masatoshi Morikawa, Yoshikuni Matsunaga, Kenji Sekine, Osamu Kagaya
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Patent number: 6492872Abstract: A high frequency power amplifier module is provided for improving output controllability. A wireless communication apparatus incorporates a high frequency power amplifier module in a multi-stage configuration including a plurality of cascaded MOSFETS. The power amplifier module comprises a bias circuit for generating a gate voltage in response to a power control voltage (vapc) generated based on a power control signal of the wireless communication apparatus. The gate voltage has a bias pattern which presents smaller fluctuations in output power in response to a control voltage (Vapc) in a region near a threshold voltage (Vth) of the MOSFETs in respective amplification stages. In this way, the controllability for the output power is improved. More specifically, the power amplifier module has a gate bias circuit for generating the gate voltage (Vg) which follows a gate voltage pattern.Type: GrantFiled: September 7, 2000Date of Patent: December 10, 2002Assignees: Hitachi, Ltd., Hitachi Tohbu Semiconductor, Ltd.Inventors: Toru Fujioka, Yoshikuni Matsunaga, Isao Yoshida, Masatoshi Morikawa, Masao Hotta, Tetsuaki Adachi