Abstract: A processor includes: a first storage that stores data stored in a main storage; a processor that outputs an instruction for loading data from the main storage into the first storage; a second storage that holds a instruction until the first storage receives the data requested by the instruction; a first controller that reads the data requested by an instruction from the first storage and transfers the requested data to the processor, when the requested data is in the first storage, or but, transfers the received instruction to the main storage, when the requested data is not in the first storage and an instruction requesting the same data as the requested data is not in the second storage; and a second controller that completes reading the data requested by an instruction, when an instruction requesting the same data as the requested data is in the second storage.

Abstract: A common L2 cache unit of a CPU constituting a multicore processor, in addition to a PFPORT arranged for each CPU core unit, has a common PFPORT shared by the plurality of the CPU core units. The common PFPORT secures an entry when the prefetch request loaded from the PFPORT into a L2 pipeline processing unit fails to be completed. The uncompleted prefetch request is loaded again from the common PFPORT to the L2 pipeline processing unit.

Abstract: A processor includes: a processing unit that has a first unit; a second unit that holds part of the data held by the first unit; a third unit that receives from the processing unit a first request including first attribute information for obtaining a first logical value and a second request including second attribute information for obtaining a second logical value and that holds the first request until receiving a completion notification of the first request or holds the second request until receiving a completion notification of the second request; and a control unit that receives the first and second requests from the third unit and, replaces the first attribute information by the second attribute information when data of the addresses corresponding to the first and second request are not in the second unit, and supplies the completion notification for the second request to the first unit.

Abstract: There is provided an acoustic processing device capable of maintaining volume and reproducing audio signals with good sound quality independent of the media audio encoding format, sound source type or sound source volume setting. In the acoustic processing device (1), a limiter control signal generation section (5) generates a limiter control signal for applying rapid variation correction determined based on a short-term signal level variation of an audio signal of a sound source and slow variation correction determined based on a long-term signal level variation of the audio signal of the sound source, and volume control sections (7) and (8) apply the generated limiter control signal to the audio signal and control the volume of the sound source.

Abstract: There is provided an acoustic processing device capable of applying acoustic processing matching listener's sense to reproduce an audio signal with satisfactory sound quality in terms of auditory sense irrespective of the characteristics of a sound source. The acoustic processing device (1) includes a gain calculation section (5) that calculates a gain correction amount corresponding to predetermined auditory sense characteristics, an offset gain calculation section (6) that calculates a gain offset based on a frequency characteristics of an audio signal analyzed by a frequency analysis section (3), an acoustic signal generation section (7) that generates an acoustic signal based on the gain correction amount and the gain offset, and an acoustic addition section (8) that adds the generated acoustic signal to the audio signal.

Abstract: A common L2 cache unit of a CPU constituting a multicore processor, in addition to a PFPORT arranged for each CPU core unit, has a common PFPORT shared by the plurality of the CPU core units. The common PFPORT secures an entry when the prefetch request loaded from the PFPORT into a L2 pipeline processing unit fails to be completed. The uncompleted prefetch request is loaded again from the common PFPORT to the L2 pipeline processing unit.

Abstract: The information processing device of the present invention stores the branch history information of a fetched instruction. When branch prediction fails, BHR information used for the branch prediction is restored using this stored branch history information. Thus, even when branch prediction fails, BHR information can be accurately restored. Accordingly, prediction accuracy can be improved.

Abstract: The information processing apparatus comprises a cache miss detection unit detects a cache miss of a load instruction; an instruction issuance stop unit stops the issuance of an instruction subsequent to a conditional branch instruction if the branch direction of a conditional branch instruction subsequent to the load instruction for which a cache miss has been detected by the cache miss detection unit is not established at the timing of issuance, wherein a period of time cancels an issued instruction, the cancelation having been caused by a branch prediction miss, is deleted and thereby a penalty for the branch prediction miss is concealed under a wait time due to a cache miss.

Abstract: The information processing device of the present invention stores the branch history information of a fetched instruction. When branch prediction fails, BHR information used for the branch prediction is restored using this stored branch history information. Thus, even when branch prediction fails, BHR information can be accurately restored. Accordingly, prediction accuracy can be improved.