Patents by Inventor Toru Hinomura

Toru Hinomura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8895431
    Abstract: A method for fabricating a semiconductor device includes: forming an interlayer insulating film on a substrate; forming a first hard mask formation film on the interlayer insulating film; altering the first hard mask formation film; after the altering of the first hard mask formation film, transferring an interconnect groove pattern to the altered first hard mask formation film to form a first hard mask made of the altered first hard mask formation film; and etching the interlayer insulating film using the first hard mask to form an interconnect groove in the interlayer insulating film. The first hard mask formation film is made of a metal film or a metallic compound film.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: November 25, 2014
    Assignee: Panasonic Corporation
    Inventors: Takeshi Harada, Toru Hinomura, Naoki Torazawa, Tatsuya Kabe
  • Patent number: 8344508
    Abstract: A semiconductor device includes: a metal-containing compound layer on a semiconductor substrate; a dielectric film on the semiconductor substrate and the metal-containing compound layer; a contact hole penetrating through the dielectric film to reach the metal-containing compound layer; a contact plug in the contact hole. The semiconductor device further includes a manganese oxide layer extending between the contact plug and respective one of the dielectric film and the metal-containing compound layer.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: January 1, 2013
    Assignee: Panasonic Corporation
    Inventor: Toru Hinomura
  • Publication number: 20100308471
    Abstract: An electronic device includes: a first substrate; and a second substrate on which the first substrate is mounted and which is electrically connected to the first substrate in at least one predetermined area. The predetermined area includes at least two through vias running through the first substrate, and an interconnect provided in the second substrate. The at least two through vias are electrically connected together via the interconnect.
    Type: Application
    Filed: August 17, 2010
    Publication date: December 9, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Hayato Korogi, Toru Hinomura, Atsushi Nishimura
  • Publication number: 20100244260
    Abstract: A semiconductor device includes: a first insulting film formed on a semiconductor substrate; a contact including a conductive film buried in the first insulating film to reach the semiconductor substrate; and a first barrier layer including a high melting point metal, formed between the semiconductor substrate and the conductive film and between the first insulating film and the conductive film. The device also includes a second barrier layer lower in moisture permeability than the first barrier layer, formed between the first barrier layer and the conductive film.
    Type: Application
    Filed: June 7, 2010
    Publication date: September 30, 2010
    Applicant: Panasonic Corporation
    Inventor: Toru HINOMURA
  • Publication number: 20100244251
    Abstract: A semiconductor device includes a first semiconductor chip, an electrode pad formed in an upper surface portion of the first semiconductor chip, a second semiconductor chip formed on the first semiconductor chip, and a through-via formed in the second semiconductor chip. A hollowed portion is formed in the electrode pad, and a bottom portion of the through-via is embedded in the hollowed portion.
    Type: Application
    Filed: June 10, 2010
    Publication date: September 30, 2010
    Applicant: Panasonic Corporation
    Inventors: Naoki TORAZAWA, Toru Hinomura
  • Publication number: 20090283910
    Abstract: A semiconductor device includes: a metal-containing compound layer on a semiconductor substrate; a dielectric film on the semiconductor substrate and the metal-containing compound layer; a contact hole penetrating through the dielectric film to reach the metal-containing compound layer; a contact plug in the contact hole. The semiconductor device further includes a manganese oxide layer extending between the contact plug and respective one of the dielectric film and the metal-containing compound layer.
    Type: Application
    Filed: July 22, 2009
    Publication date: November 19, 2009
    Applicant: PANASONIC CORPORATION
    Inventor: Toru HINOMURA
  • Patent number: 7233073
    Abstract: After forming a hole in an insulating film, a first tungsten film is formed over the wall and bottom surfaces of the hole. Then, a second tungsten film is formed by using the first tungsten film as a seed layer to fill up the hole. When the first tungsten film is formed, the average value of the diameters of crystal grains of the portion of the first tungsten film which is formed on the bottom surface of the hole is suppressed to 30 nm or less.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: June 19, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Atsushi Nishimura, Toru Hinomura, Atsushi Ikeda, Takenobu Kishida
  • Publication number: 20050023702
    Abstract: After forming a hole in an insulating film, a first tungsten film is formed over the wall and bottom surfaces of the hole. Then, a second tungsten film is formed by using the first tungsten film as a seed layer to fill up the hole. When the first tungsten film is formed, the average value of the diameters of crystal grains of the portion of the first tungsten film which is formed on the bottom surface of the hole is suppressed to 30 nm or less.
    Type: Application
    Filed: April 23, 2004
    Publication date: February 3, 2005
    Inventors: Atsushi Nishimura, Toru Hinomura, Atsushi Ikeda, Takenobu Kishida
  • Patent number: 6746962
    Abstract: A first metal film is deposited on a bottom and a wall of a recess formed in an insulating film on a semiconductor substrate. A second metal film is filled in the recess on the first metal film. The second metal film is formed from a polycrystalline tungsten film having a crystal plane of a (110) orientation.
    Type: Grant
    Filed: October 18, 2001
    Date of Patent: June 8, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takenobu Kishida, Takeshi Harada, Toru Hinomura, Hiromitsu Abe, Mitsunari Satake, Kenichi Kunimitsu
  • Publication number: 20020050648
    Abstract: A first metal film is deposited on a bottom and a wall of a recess formed in an insulating film on a semiconductor substrate. A second metal film is filled in the recess on the first metal film. The second metal film is formed from a polycrystalline tungsten film having a crystal plane of a (110) orientation.
    Type: Application
    Filed: October 18, 2001
    Publication date: May 2, 2002
    Inventors: Takenobu Kishida, Takeshi Harada, Toru Hinomura, Hiromitsu Abe, Mitsunari Satake, Kenichi Kunimitsu