Abstract: A side channel attack resistance evaluation apparatus includes: a measurement section that measures side channel information leaking from an encryption device to be evaluated; a noise removal section that removes noise from the measured side channel information using a band-pass filter (BPF); a passband determination section that determines the passband of the band-pass filter; and a DSCA (Differential Side-Channel Analysis) evaluation section that evaluates resistance against the differential side channel analysis. The passband determination section preferably has a DFT processing section and a power spectrum analysis section, or has a DFT processing and a DFA processing section.

Abstract: A side channel attack resistance evaluation apparatus includes: a measurement section that measures side channel information leaking from an encryption device to be evaluated; a noise removal section that removes noise from the measured side channel information using a band-pass filter (BPF); a passband determination section that determines the passband of the band-pass filter; and a DSCA (Differential Side-Channel Analysis) evaluation section that evaluates resistance against the differential side channel analysis. The passband determination section preferably has a DFT processing section and a power spectrum analysis section, or has a DFT processing and a DFA processing section.

Abstract: Provided is a side channel attack tolerance evaluation device capable of evaluating the propriety of the estimation of an encryption algorism, processing timing, and determination of a processing sequence of the encryption algorism using side channel information. The side channel attack tolerance evaluation device, which performs evaluation of tolerance to a side channel attack by using side channel information leaking from an encryption device, is provided with a storage unit (character data storage device), a measurement unit (side channel information measurement device), and a processing unit (side channel attack tolerance evaluation unit). The storage unit stores side channel information that has been previously acquired by executing a predetermined encryption algorithm in an encryption device or information obtained by applying predetermined processing to the side channel information. The measurement unit measures the side channel information generated from an encryption device to be evaluated.

Abstract: A pseudo-random number generation device having a resistance against attack methods that use the number of operations of an LFSR, a stream encryption device, and a program are provided. The stream encryption device has: means (delay means 811 to 81N) which exclusively operate with each LFSR (801 to 80N) in the pseudo-random number generator, that is of a clock control type, and makes uniform the generation processing time or the power consumption of one output unit; or means which randomizes the generation processing time or the power consumption power of one output unit.

Abstract: The bit strings of multipliers B and N are converted through the use of the Booth's algorithm in units composed of a predetermined number of bits and the operation of A×B+u×N is executed by a carry save adder using the value of an integral multiple of multiplicand A corresponding to the multiplication result of the values of the converted multiplier B and multiplicand A and also the value of an integral multiple of multiplicand u corresponding to the multiplication result of the values of the converted multiplier N and multiplicand u. The operation result of A×B+u×N supplied from the carry save adder are added to the operation result in the past of A×B+u×N through the use of an adder and the added result is supplied as the result of a modular-multiplication operation S=S+A×B+u×N.

Abstract: Either a multiplicand A or 0 is selected, depending on the value of multiplier B supplied in a unit composed of q bits through the use of selectors, and the selected result is provided, and either a multiplicand u or 0 is selected, depending on the value of multiplier N supplied in a unit composed of q bits through the use of selectors, and the selected result is provided. A carry save adder implements the operation of A×B+u×N making use of the values successively supplied from the selectors. To the operation result of A×B+u×N supplied from the carry save adder in a unit composed of q bits is added the operation result of A×B+u×N in the past supplied in a unit composed of q bits and the added result is issued as a result of the modular-multiplication operation S.