Abstract: A wiring substrate includes a first insulating layer, an electronic component, a resin layer, a second insulating layer, a wiring pattern, and a via interconnect. The first insulating layer includes a cavity. The electronic component includes a first surface at which a pad is formed and a second surface facing away from the first surface and fixed in the cavity via an adhesive layer. The resin layer is on the first surface of the electronic component and covers the pad. The second insulating layer is on the first insulating layer and covers the resin layer. The wiring pattern is on the second insulating layer. The via interconnect pierces through the second insulating layer and the resin layer to electrically connect the wiring pattern to the pad.

Abstract: A wiring substrate includes a first insulating layer, an electronic component, a resin layer, a second insulating layer, a wiring pattern, and a via interconnect. The first insulating layer includes a cavity. The electronic component includes a first surface at which a pad is formed and a second surface facing away from the first surface and fixed in the cavity via an adhesive layer. The resin layer is on the first surface of the electronic component and covers the pad. The second insulating layer is on the first insulating layer and covers the resin layer. The wiring pattern is on the second insulating layer. The via interconnect pierces through the second insulating layer and the resin layer to electrically connect the wiring pattern to the pad.

Abstract: According to one embodiment, there is provided a semiconductor package including: a semiconductor chip; a resin portion formed to cover the semiconductor chip; a wiring structure formed on the resin portion and electrically connected to the semiconductor chip; and a warpage preventing member provided above the resin portion to have a thermal expansion coefficient closer to that of the semiconductor chip than to that of the wiring structure.

Abstract: According to one embodiment, there is provided a semiconductor package including: a semiconductor chip; a resin portion formed to cover the semiconductor chip; a wiring structure formed on the resin portion and electrically connected to the semiconductor chip; and a warpage preventing member provided above the resin portion to have a thermal expansion coefficient closer to that of the semiconductor chip than to that of the wiring structure.

Abstract: A manufacturing method includes forming a semi-cured insulation layer made of a photosensitive material on a supporting body; forming an opening part in the insulation layer by a photolithography method, the opening part being configured to expose the supporting body; arranging a semiconductor chip on the insulation layer so that a position of an electrode of the semiconductor chip is consistent with a position of the opening part, and curing the insulation layer; forming sealing resin on a surface of the insulation layer at the semiconductor chip side, the sealing resin being configured to seal the semiconductor chip; removing the supporting body; and providing a wiring layer on a surface of the insulation layer opposite to the semiconductor chip side, the wiring layer being electrically connected to the electrode exposed in the opening part, so that a wiring structural body including the insulation layer and the wiring layer is formed.

Abstract: A manufacturing method includes forming a semi-cured insulation layer made of a photosensitive material on a supporting body; forming an opening part in the insulation layer by a photolithography method, the opening part being configured to expose the supporting body; arranging a semiconductor chip on the insulation layer so that a position of an electrode of the semiconductor chip is consistent with a position of the opening part, and curing the insulation layer; forming sealing resin on a surface of the insulation layer at the semiconductor chip side, the sealing resin being configured to seal the semiconductor chip; removing the supporting body; and providing a wiring layer on a surface of the insulation layer opposite to the semiconductor chip side, the wiring layer being electrically connected to the electrode exposed in the opening part, so that a wiring structural body including the insulation layer and the wiring layer is formed.

Abstract: The present disclosure relates to a method of manufacturing a wiring board. The method includes: (a) preparing a first board having a pad; (b) providing an insulating member on the first board, wherein a size of the insulating member is larger than that of the first board, when viewed from the top; (c) forming a via in the insulating member such that the via is directly connected to the pad; and (d) repeatedly forming a wiring layer and an insulating layer on the insulating member in which the via is formed, thereby forming a second board.

Abstract: In a method for manufacturing a semiconductor device having a plate-shaped member, a semiconductor element, and a wiring board, the manufacturing method for the semiconductor device includes: a concave portion forming step (S101) of the plate-shaped member; a semiconductor element provisionally adhering step (S102) for provisionally adhering the semiconductor element to a portion located in the vicinity of a first corner portion of a concave portion; a semiconductor element aligning step (S103) for aligning the semiconductor element based upon thermal expansion of a semiconductor element depressing member; a resin molding step (S104) of the plate-shaped member; an electrode pad exposing step (S105) for exposing an electrode pad by grinding the plate-shaped member; and a wiring board stacking step (S106) for stacking layers by directly connecting the exposed electrode pad to the wiring layer on the ground plane of the plate-shaped member.

Abstract: The present disclosure relates to a method of manufacturing a wiring board. The method includes: (a) preparing a first board having a pad; (b) providing an insulating member on the first board, wherein a size of the insulating member is larger than that of the first board, when viewed from the top; (c) forming a via in the insulating member such that the via is directly connected to the pad; and (d) repeatedly forming a wiring layer and an insulating layer on the insulating member in which the via is formed, thereby forming a second board.

Abstract: In a semiconductor device, a semiconductor element is built into a resin molded part molded in a flat plate shape. A wiring is electrically connected to the semiconductor element and is disposed on one surface of the resin molded part so that an inner surface side of the wiring is sealed with the resin molded part and an outer surface of the wiring is exposed flush with the one surface of the resin molded part. An electrode is disposed on the wiring in an outside of a plane area of the semiconductor element and extends through the resin molded part in a thickness direction. A tip part of the electrode protrudes from the other surface of the resin molded part.

Abstract: A semiconductor device is provided which is capable of improving the productivity, the reliably, and the shielding of exposed parts such as leads or others and preventing chipping.

Abstract: A semiconductor device is provided which is capable of improving the productivity, the reliably, and the shielding of exposed parts such as leads or others and preventing chipping.