Patents by Inventor Toru Ido

Toru Ido has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060017596
    Abstract: Transient response generating circuit A has a first circuit 3 that generates transient response OUT1 in a first polarity direction, a second circuit 4 that generates transient response OUT2 in a second polarity direction opposite to the first polarity, and a transient response synthesizing circuit 6 that combines the transient response OUT1 in the first polarity direction and the transient response OUT2 in the second polarity direction to generate composite transient response OUTC.
    Type: Application
    Filed: June 29, 2005
    Publication date: January 26, 2006
    Inventors: Toru Ido, Soichiro Ishizuka
  • Publication number: 20060007027
    Abstract: A digital encoder having a dynamic element matching (DEM) processor is divided into a master DEM circuit and N slave DEM circuits. The master DEM circuit encodes a multibit digital input signal (INO) into parallel codes (C1) corresponding to the coefficient of a plurality of output nodes on the basis of a prescribed DEM algorithm. Each of the N slave DEM means (2) has 3 or more output nodes. Code (C1) from the master DEM circuit is encoded into parallel codes (C2) with the same weighting for each code and corresponding to the configuration of the 3 or more output nodes on the basis of a prescribed DEM algorithm, and the obtained parallel codes are output in parallel from 3 or more output nodes.
    Type: Application
    Filed: June 29, 2005
    Publication date: January 12, 2006
    Inventors: Soichiro Ishizuka, Toru Ido