Patents by Inventor Toru Kaga
Toru Kaga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 5739589Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel sType: GrantFiled: June 3, 1996Date of Patent: April 14, 1998Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
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Patent number: 5700705Abstract: The manufacture of a memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. The manufacture of each load MISFET consists of forming source, drain and channel regions within the same polycrystalline silicon film, and a gate electrode consisting of a different layer conductive film, such as a polycrystalline film, than that of the drive MISFETs. The manufacture of the memory cell having such a stacked arrangement, facilitates the patterning of the source (drain) region and gate electrode of each load MISFET thereof to have an overlapping relationship with each other so as to increase the effective capacitance associated with each of the memory cell storage nodes.Type: GrantFiled: June 6, 1995Date of Patent: December 23, 1997Assignee: Hitachi, Ltd.Inventors: Satoshi Meguro, Kiyofumi Uchibori, Norio Suzuki, Makoto Motoyoshi, Atsuyoshi Koike, Toshiaki Yamanaka, Yoshio Sakai, Toru Kaga, Naotaka Hashimoto, Takashi Hashimoto, Shigeru Honjou, Osamu Minato
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Patent number: 5646423Abstract: A memory cell of the type a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETS. Each load MISFET of a memory cell consists of a source, drain and channel region formed within the same polycrystalline silicon film, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. In a memory cell having such a stacked arrangement, the source (drain) region and gate electrode of each load MISFET thereof are patterned to have an overlapping relationship with each other so as to increase the effective capacitance associated with each of the memory cell storage nodes.Type: GrantFiled: June 6, 1995Date of Patent: July 8, 1997Assignee: Hitachi, Ltd.Inventors: Satoshi Meguro, Kiyofumi Uchibori, Norio Suzuki, Makoto Motoyoshi, Atsuyoshi Koike, Toshiaki Yamanaka, Yoshio Sakai, Toru Kaga, Naotaka Hashimoto, Takashi Hashimoto, Shigeru Honjou, Osamu Minato
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Patent number: 5619055Abstract: A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. In a memory cell having such a stacked arrangement, the source region and gate electrode of each load MISFET thereof are patterned to have a widely overlapping relationship with each other to form a capacitor element thereacross such that an increase in the overall capacitance associated with each of the memory cell storage nodes is effected thereby decreasing occurrence of soft error.Type: GrantFiled: April 27, 1995Date of Patent: April 8, 1997Assignee: Hitachi, Ltd.Inventors: Satoshi Meguro, Kiyofumi Uchibori, Norio Suzuki, Makoto Motoyoshi, Atsuyoshi Koike, Toshiaki Yamanaka, Yoshio Sakai, Toru Kaga, Naotaka Hashimoto, Takashi Hashimoto, Shigeru Honjou, Osamu Minato
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Patent number: 5591998Abstract: A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.Type: GrantFiled: May 17, 1995Date of Patent: January 7, 1997Assignee: Hitachi, Ltd.Inventors: Shinichiro Kimura, Naotaka Hashimoto, Yoshio Sakai, Tokuo Kure, Yoshifumi Kawamoto, Toru Kaga, Eiji Takeda
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Patent number: 5583358Abstract: A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.Type: GrantFiled: October 17, 1994Date of Patent: December 10, 1996Assignee: Hitachi, Ltd.Inventors: Shinichiro Kimura, Naotaka Hashimoto, Yoshio Sakai, Tokuo Kure, Yoshifumi Kawamoto, Toru Kaga, Eiji Takeda
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Patent number: 5557147Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel sType: GrantFiled: April 19, 1994Date of Patent: September 17, 1996Assignees: Hitachi, Ltd., Hitachi ULSI Engineering CorporationInventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
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Patent number: 5523965Abstract: Short and long sides of each of capacitors held by a semiconductor memory device are respectively made shorter and longer so that the capacitors are laid over memory cell regions adjacent to each other. Thus, large capacity type capacitors whose circumferential length increases and total capacitor area greatly increases can be obtained without so increasing plane areas of the capacitors.Type: GrantFiled: December 22, 1994Date of Patent: June 4, 1996Assignee: Hitachi, Ltd.Inventors: Toru Kaga, Shoji Shukuri, Masahiro Moniwa, Dai Hisamoto
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Patent number: 5483083Abstract: A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is provided in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconductor strip, such as a polycrystalline silicon film strip, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. A wiring line, formed as a separate conductive layer, is provided in the stacking arrangement of the drive and load MISFETs of a memory cell for applying a ground potential to source regions of the drive MISFETs thereof.Type: GrantFiled: March 9, 1993Date of Patent: January 9, 1996Assignee: Hitachi, Ltd.Inventors: Satoshi Meguro, Kiyofumi Uchibori, Norio Suzuki, Makoto Motoyoshi, Atsuyoshi Koike, Toshiaki Yamanaka, Yoshio Sakai, Toru Kaga, Naotaka Hashimoto, Takashi Hashimoto, Shigeru Honjou, Osamu Minato
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Patent number: 5466621Abstract: A semiconductor device such as FET or charge coupled device, having a channel or a charge coupled portion provided in a thin semiconductor layer which is nearly perpendicular to the substrate and to which the necessary electrode such as the gate electrode and the necessary insulating layer are added can maintain the necessary amount of electric current by securing the height of the semiconductor layer and also can have its plane size reduced minutely. Further, the semiconductor memory device using the above semiconductor device is suitable to high integration and has excellent electric characteristics.Type: GrantFiled: October 25, 1993Date of Patent: November 14, 1995Assignee: Hitachi, Ltd.Inventors: Dai Hisamoto, Toru Kaga, Shinichiro Kimura, Masahiro Moniwa, Haruhiko Tanaka, Atsushi Hiraiwa, Eiji Takeda
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Patent number: 5374576Abstract: A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacity portions to be arranged very densely and a sufficiently large capacity to be maintained with very small cell areas. Since the storage capacity portions are formed even on the bit lines, the bit lines are shielded, so that the capacity decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacity portion so that a part of thereof has a form of a wall substantially vertical to the substrate in order to increase the capacity.Type: GrantFiled: June 3, 1993Date of Patent: December 20, 1994Assignee: Hitachi, Ltd.Inventors: Shinichiro Kimura, Naotaka Hashimoto, Yoshio Sakai, Tokuo Kure, Yoshifumi Kawamoto, Toru Kaga, Eiji Takeda
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Patent number: 5349218Abstract: A semiconductor integrated circuit device has a semiconductor memory cell array including word lines, data lines and a plurality of memory cells provided at cross points of the word and data lines. Each memory cell has a cell selection transistor and an information storage capacitor connected in series. The cell selection transistor in one cell includes first and second doped regions formed in a main surface of a semiconductor substrate, a first insulating film formed on the main surface between the first and second doped regions and a control electrode layer formed on the first insulating film between the first and second doped regions. The first doped region is connected with a data line, while the control electrode is connected with a word line.Type: GrantFiled: April 29, 1992Date of Patent: September 20, 1994Assignees: Hitachi, Ltd., Texas Instruments Japan, Inc.Inventors: Yoshitaka Tadaki, Toshihiro Sekiguchi, Hiroyuki Uchiyama, Toru Kaga, Jun Murata, Osaomi Enomoto
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Patent number: 5346834Abstract: An improved method for manufacturing an insulated gate field effect transistor is provided. As a first step, a silicon oxide film is grown on a silicon substrate, and a first silicon nitride film is deposited thereon. The first silicon nitrite film, the silicon oxide film and the silicon substrate are then etched using a resist pattern as a mask to form a silicon island which includes at least a part of the silicon substrate. A second silicon oxide film is then grown on the surface of the silicon substrate exposed by the second step, as well as on the surface of the silicon island, and a second silicon nitrite film is deposited thereon. The second silicon nitrite film is then etched to leave a portion of the second silicon nitrite film deposited on a side wall of the silicon island. After this, a third silicon oxide film is grown by thermal oxidation of the surface of the silicon substrate to electrically separate the silicon island from the silicon substrate.Type: GrantFiled: March 3, 1992Date of Patent: September 13, 1994Assignee: Hitachi, Ltd.Inventors: Dai Hisamoto, Toru Kaga, Shinichiro Kimura, Masahiro Moniwa, Haruhiko Tanaka, Atsushi Hiraiwa, Eiji Takeda
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Patent number: 5331191Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel sType: GrantFiled: September 30, 1992Date of Patent: July 19, 1994Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
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Patent number: 5202275Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel sType: GrantFiled: March 20, 1990Date of Patent: April 13, 1993Assignees: Hitachi Ltd., Hitachi VLSI Engineering Corp.Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
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Patent number: 5200635Abstract: The present invention concerns a semiconductor device having a low-resistivity wiring structure. Wirings formed directly on a hill and valley structure result in a thin portion and, in an extreme case, a disconnected portion. This increases the resistivity of wirings on the hill and valley structure and lowers the reliability of the connection. In a case where the wirings are data lines of a memory, with an increased effective length, the resistance and the parasitic capacitance of the data line is greater. The above mentioned problems have been solved by wirings which comprise at least two layers of conductive film including a first conductive film as a lower layer and a second conductive film as an upper layer, and the first conductive layer has a surface moderating or planarizing the hills and valleys in the underlying material.Type: GrantFiled: April 17, 1991Date of Patent: April 6, 1993Assignee: Hitachi, Ltd.Inventors: Toru Kaga, Shinichiro Kimura, Katsutaka Kimura, Yoshinobu Nakagome, Digh Hisamoto, Yoshifumi Kawamoto, Eiji Takeda, Shimpei Iijima, Tokuo Kure, Takashi Nishida
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Patent number: 5196910Abstract: A semiconductor memory wherein a memory cell region having a plurality of memory cells and a relatively high altitude above the surface of semiconductor substrate is formed at a recessed part of the semiconductor substrate having the recessed part and a projected part, and wherein a peripheral circuit region having a comparatively low altitude from the surface of the semiconductor substrate is formed at the projected part of the semiconductor substrate.Type: GrantFiled: February 4, 1991Date of Patent: March 23, 1993Assignee: Hitachi, Ltd.Inventors: Noboru Moriuchi, Yoshiki Yamaguchi, Toshihiko Tanaka, Norio Hasegawa, Yoshifumi Kawamoto, Shin-ichiro Kimura, Toru Kaga, Tokuo Kure
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Patent number: 5194749Abstract: In a memory cell of SRAM of CMOS type, load MISFET having a polycrystalline silicon film as area of source, drain and channel is stacked on drive MISFET, and gate electrodes of the drive MISFET and the load MISFET are constituted by conductive films in different layers. Area of source and drain provided on the polycrystalline silicon film has an overlapped area with the gate electrode of the load MISFET.Type: GrantFiled: February 19, 1992Date of Patent: March 16, 1993Assignee: Hitachi, Ltd.Inventors: Satoshi Meguro, Kiyofumi Uchibori, Norio Suzuki, Makoto Motoyoshi, Atsuyoshi Koike, Toshiaki Yamanaka, Yoshio Sakai, Toru Kaga, Naotaka Hashimoto, Takashi Hashimoto, Shigeru Honjou, Osamu Minato
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Patent number: 5177576Abstract: A vertical semiconductor memory device is provided which capable of miniaturization. More particularly, a memory cell is provided having a trench capacitor and a vertical transistor in a dynamic random access memory suitable for high density integration. An object of this arrangement is to provide a vertical memory cell capable of miniaturization for use in a ultra-high density integration DRAM of a Gbit class. This memory cell is characterized in that each memory cell is covered with an oxide film, an impurity area does not exist on the substrate side, an area in which a channel area is formed is a hollow cylindrical single crystal area, connection of impurity areas as source-drain areas and bit lines and the electrode of a capacitor is made by self-alignment and connection between a word line electrode and a gate electrode is also made by self-alignment.Type: GrantFiled: May 6, 1991Date of Patent: January 5, 1993Assignee: Hitachi, Ltd.Inventors: Shin'ichiro Kimura, Tokuo Kure, Toru Kaga, Digh Hisamoto, Eiji Takeda
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Patent number: 5140389Abstract: A semiconductor memory device having STC cells wherein the major portions of active regions consisting of channel-forming portions are inclined at an angle of 45 degrees with respect to word lines and bit lines that meet at right angles with each other, thereby enabling the storage capacitor portions to be arranged very densely and a sufficiently large capacitance to be maintained with very small cell areas. Since the storage capacitor portions are formed even on the bit lines, the bit lines are shielded, so that the capacitance decreases between the bit lines and, hence, the memory array noise decreases. It is also possible to design the charge storage capacitor portion so that a part thereof is in the form of a wall substantially vertical to the substrate in order to increase the capacitance.Type: GrantFiled: February 5, 1990Date of Patent: August 18, 1992Assignee: Hitachi, Ltd.Inventors: Shinichiro Kimura, Naotaka Hashimoto, Yoshio Sakai, Tokuo Kure, Yoshifumi Kawamoto, Toru Kaga, Eiji Takeda