Abstract: Provided is a conductive undercoating agent, including: a conductive carbon material; a binding agent; and a solvent, wherein the conductive carbon material is flaked graphite having an average thickness of from 10 nm to 200 nm and a specific surface area of from 10 m2/g to 40 m2/g.

Abstract: In order to reduce the time required for error correction in the error correction device, data are transferred from the buffer memory not only to the syndrome calculator but also to the error detector at the same time, and until the syndrome calculator detects an error-containing code, the error detector performs error detection in parallel with the syndrome calculation done by the syndrome calculator. In the error detection after the error corrector corrects the error, the mid-term results of the error detection obtained before the error-containing code is detected are used. Consequently, it becomes unnecessary to transfer all data from the buffer memory to the error detector, thereby making it possible to execute error detection process at a halfway point.

Abstract: For reducing time required for error correction in an error correction device, data are transferred from a buffer memory not only to a syndrome calculator but also to an error detector at the same time, and until the syndrome calculator detects an error-containing code, the error detector performs error detection in parallel with the syndrome calculation done by the syndrome calculator. During error detection after the error corrector corrects the error, mid-term results of the error detection obtained before an error-containing code is detected are used. Consequently, it becomes unnecessary to transfer all data from the buffer memory to the error detector, thereby making execution of an error detection process possible at a halfway point.

Abstract: In a data processing unit, improvement of the writing speed and efficiency of demodulated data from demodulating means into the buffer memory is achieved. As solving means thereof, writing of data demodulated in the demodulating means into the buffer memory is continuously performed after waiting for arrival of data of the same kind. Therefore, upon transfer of the demodulated data from the demodulating circuit to a temporary storage sub-means within the bus controller which controls access to the buffer memory, the kind of data of the next demodulated data is also transmitted.

Abstract: A semiconductor for having a reduced required number of probes for inputting burn-in data to a target circuit, including two separate scan chains having respective first and second input terminals, and a selector for selecting one of first data from a first input terminal and second data from a second input terminal and supplying the selected first and second data to the second scan chain.

Abstract: In order to reduce the time required for error correction in the error correction device, data are transferred from the buffer memory not only to the syndrome calculator but also to the error detector at the same time, and until the syndrome calculator detects an error-containing code, the error detector performs error detection in parallel with the syndrome calculation done by the syndrome calculator. In the error detection after the error corrector corrects the error, the mid-term results of the error detection obtained before the error-containing code is detected are used. Consequently, it becomes unnecessary to transfer all data from the buffer memory to the error detector, thereby making it possible to execute error detection process at a halfway point.

Abstract: In a data processing unit, improvement of the writing speed and efficiency of demodulated data from demodulating means into the buffer memory is achieved. As solving means thereof, writing of data demodulated in the demodulating means into the buffer memory is continuously performed after waiting for arrival of data of the same kind. Therefore, upon transfer of the demodulated data from the demodulating circuit to a temporary storage sub-means within the bus controller which controls access to the buffer memory, the kind of data of the next demodulated data is also transmitted.

Abstract: In the memory exclusive control device having a CPU-1 accessible to both a common memory and first memory devices, the CPU-1 is prohibited from accessing to the common memory device (105) during OFF state of an access permission flag, and when the access permissive flag ON is established by TCS (111), the gate of the access permitting unit (103) is opened to thereby permit the CPU-1 to access to the common memory device (105). Thus, the memory exclusive control can be realized for transferring a desired program to be processed to the address space of the first memory device, allowing omission of a third memory device.

Abstract: A control system for controlling a cache tag memory has an address conversion device which includes an associative storage for storing logical addresses, a random access memory for storing physical addresses, and a hit-signal generating circuit for generating a hit signal, a word selecting signal and at least one control signal. The hit signal indicates that a hit has occurred between a logical address stored in the associative storage and an input logical address. The address conversion device controls the reading operation of a tag address stored in the cache tag memory by using the control signal generated by the hit-signal generating circuit in synchronization with a word selecting signal used in the reading operation of a physical address stored in the random access memory such that the physical address and the tag address are read at substantially the same time.

Abstract: The clock generator of this invention includes: an input shutoff control circuit for receiving a base clock and a reference clock and outputting a first signal and a second signal in response to a reset signal, a phase comparator for outputting a phase difference signal indicating a phase difference between the first signal and the second signal; a voltage control oscillator for outputting a frequency variable clock in correspondence with the phase difference signal; and a voltage fixing control circuit for controlling a voltage of the phase difference signal in response to the reset signal, wherein, when the reset signal is in a first level, the input shutoff control circuit: outputs the base clock to the phase comparator as the first signal and outputs the reference clock to the phase comparator as the second signal, and the voltage fixing control circuit holds the voltage of the phase difference signal, and when the reset signal is in a second level different from the first level, the input shutoff control

Abstract: In a processor having a central processing unit, an instruction cache and a data cache, a bus controller is provided for controlling giving and receiving of a signal between internal instruction and data buses and external bus. Upon concurrent miss of instruction cache and data cache, the bus controller executes an external instruction access with priority in case where the external instruction access is a same page access as a previous external DRAM access, and executes an external data access in the other cases. Thereby, the cycle number required for the external access is reduced, while reducing the number of instruction execution cycles as a total.

Abstract: This an arithmetic processor which represents internal arithmetic operands as signed-digit numbers, each digit of which may have either positive, zero, or negative values and which executes addition of a plurality of numbers each of whose most significant digit is offset with respect to the other numbers. The arithmetic processor includes an adder tree which is so constituted that a pair of said plurality of numbers are added to obtain a partial sum and further pairs of partial sums are successively added to obtain a final sum of all numbers.

Abstract: This invention discloses an arithmetic processor which represents internal arithmetic operands as signed-digit numbers, each digit of which may have either positive, zero, or negative values and which executes addition of a plurality of numbers each of whose most significant digit is offset with respect to the other numbers. The arithmetic processor includes an adder tree which is so constituted that a pair of said plurality of numbers are added to obtain a partial sum and further pairs of partial sums are successively added to obtain a final sum of all numbers.