Abstract: A method for a path trace check reducing a load on a computer, raising the speed of the check, and easily enabling an increase of nodes to be added. On a sender side, a first computer simply generates path trace data, adds a specific code CR to this, multiplexes this to the transmission data, then transmits the same to a transmission line. On a receiver side, a second computer simply generates an expected value of the path trace data, autonomously compares this expected value and the actual path trace data extracted from the received transmission data by using the specific code, and determines coincidence of the two.

Abstract: A digital communication network has a first end office which includes a first multiplexer unit and a second end office which includes a second multiplexer unit. The network performs transmission and reception of multiplexed signals between the first end office and the second end office. A monitor unit is provided within the first end office. Monitoring is performed of the accuracy of the signal received by the second end office from the first end office, signal accuracy information with regard to the received signal being included as subsignalling information in the input signal Sin which is input to the first end office from the second end office. The subsignalling information is extracted by the monitor unit from the input signal, so as to enable monitoring of the signal accuracy of the input signal. The result is a significant improvement in the improvement of transmission quality monitoring service provided in the digital communication network.

Abstract: A digital cross connect system includes reception interface parts for converting an input line signal into a VT signal having a VT frame format in conformance with synchronous optical network (SONET) standards, a switching part for cross connecting the VT signal received from the reception interface parts, and transmission interface parts for converting the cross connected VT signal received from the switching parts into a line signal. The reception interface part inserts a frame synchronizing signal within a reserved path overhead part of the VT signal, and the transmission interface part achieves frame synchronization of the VT signal in response to the frame synchronizing signal.

Abstract: A zero string error detection circuit which detects a specified number of zeros occurring in succession in bipolar data. The detection circuit has a relatively small gate size achieved by making the shift registers in the B8ZS or B6ZS code conversion circuit serve also for zero string monitoring. The zero string error detection circuit includes a pair of shift registers which receive serial bipolar data and convert it to parallel data composed of a specified number of bits, a code detector which, upon detecting a specific code from the parallel outputs of the shift registers, issues a reset signal to the shift registers to make the outputs of the shift registers zero, a zero string monitor which issue a zero string error detection signal when the outputs of the shift registers become zero, and a gate which inhibits the zero string monitor from issuing the zero string error detection signal during a specific period when the code detector issues a reset signal.

Abstract: A B8ZS.B6ZS coding circuit commonly used for a B8ZS coding or a B6ZS coding, generating a B8ZS violation signal or a B6ZS violation signal at a same start timing, and formed by a smaller circuit. The B8ZS.

Abstract: A digital data multiple conversion system which can be used in a digital data communication network and recover lost clock pulses.

Abstract: A system for controlling a change of sequence order of channel data for a telecommunication terminal device including: a plurality of channel boards provided to a terminal device and each having transmitting and receiving portions; a multiplexing portion for multiplexing data sent from the channel boards so as to generate transmission data; a demultiplexing portion for demultiplexing reception data so as to send it to the channel boards; and a sequence order address signal generator for generating a sequence order address signal to a memory.