Patents by Inventor Toru Kurosaki

Toru Kurosaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7855413
    Abstract: A transistor and diode having a low resistance and a high breakdown voltage are provided. When the bottom portion of a narrow trench having the shape of a rectangular parallelepiped is filled with a semiconductor grown by epitaxial method, a {1 0 0} plane is exposed at the sidewalls of the narrow trench. The semiconductor is epitaxially grown at a constant rate on each sidewall of the narrow trench; thereby, creating a filling material with no voids present therein. The concentration and width of the filling material are optimized. This allows the portion located between the filling materials in a drain layer to be completely depleted when the filling material is completely depleted; thereby, making it possible to establish an electric field having a constant strength in the depletion layer extended in the drain layer.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: December 21, 2010
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Mizue Kitada, Kosuke Oshima, Toru Kurosaki, Shinji Kunori, Akihiko Sugai
  • Patent number: 7365391
    Abstract: A semiconductor device having high withstand voltage is provided. An active groove 22a includes a long and narrow main groove part 26 and a sub groove part 27 connected to a longitudinal side surface of the main groove part, and a buried region 24 of a second conductivity type whose height is lower than the bottom surface of the base diffusion region 32a of the second conductivity type is provided on the bottom surface of the main groove part 26. An active groove filling region 25 of the second conductivity type in contact with the base diffusion region 32a is provided in the sub groove part 27. The buried region 24 is contacted to the base diffusion region 32a through the active groove filling region 25. Since one gate groove 83 is formed by the part above the buried region 24 in one active groove 22a, the gate electrode plugs 48 are not separated, which allows the electrode pattern to be simplified.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: April 29, 2008
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Toru Kurosaki, Shinji Kunori, Mizue Kitada, Kosuke Ohshima, Hiroaki Shishido, Masato Mikawa
  • Publication number: 20070194364
    Abstract: A transistor and diode having a low resistance and a high breakdown voltage are provided. When the bottom portion of a narrow trench having the shape of a rectangular parallelepiped is filled with a semiconductor grown by epitaxial method, a {1 0 0} plane is exposed at the sidewalls of the narrow trench. The semiconductor is epitaxially grown at a constant rate on each sidewall of the narrow trench; thereby, creating a filling material with no voids present therein. The concentration and width of the filling material are optimized. This allows the portion located between the filling materials in a drain layer to be completely depleted when the filling material is completely depleted; thereby, making it possible to establish an electric field having a constant strength in the depletion layer extended in the drain layer.
    Type: Application
    Filed: April 20, 2007
    Publication date: August 23, 2007
    Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Mizue Kitada, Kosuke Oshima, Toru Kurosaki, Shinji Kunori, Akihiko Sugai
  • Patent number: 7230298
    Abstract: A transistor and diode having a low resistance and a high breakdown voltage are provided. When the bottom portion of a narrow trench having the shape of a rectangular parallelepiped is filled with a semiconductor grown by epitaxial method, a {1 0 0} plane is exposed at the sidewalls of the narrow trench. The semiconductor is epitaxially grown at a constant rate on each sidewall of the narrow trench; thereby, creating a filling material with no voids present therein. The concentration and width of the filling material are optimized. This allows the portion located between the filling materials in a drain layer to be completely depleted when the filling material is completely depleted; thereby, making it possible to establish an electric field having a constant strength in the depletion layer extended in the drain layer.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: June 12, 2007
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Mizue Kitada, Kosuke Oshima, Toru Kurosaki, Shinji Kunori, Akihiko Sugai
  • Patent number: 7208375
    Abstract: A technique for improving a ruggedness of a transistor against breakdown is provided. In a transistor of the present invention, a height of filling regions is higher than that of buried regions, so that a withstanding voltage of the filling regions is higher than that of the buried regions. Therefore, since avalanche breakdown occurs in an active region, causing an avalanche breakdown current to flow through the active region having a large area, current concentration does not occur. As a result, a ruggedness of an element against breakdown is increased.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: April 24, 2007
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Toru Kurosaki, Hiroaki Shishido, Mizue Kitada, Shinji Kunori, Kosuke Ohshima
  • Patent number: 7196376
    Abstract: An active groove filled region 23a is kept at a portion of an active groove 22a connecting to an embedded region 24 positioned below a gate groove 83. The active groove filled region 23a connects to a source electrode film 58a so as to have the same electric potential as a source region 64. When a reverse bias is applied between a base region 32a and a conductive layer 12, a reverse bias is also applied between the embedded region 24 and the conductive layer 12; and therefore, depletion layers spread out together and a withstanding voltage is increased.
    Type: Grant
    Filed: April 4, 2005
    Date of Patent: March 27, 2007
    Assignee: Shindengen Electric Manufacturing Co., Ltd.,
    Inventors: Toru Kurosaki, Shinji Kunori, Mizue Kitada, Kosuke Ohshima, Hiroaki Shishido
  • Publication number: 20070045726
    Abstract: A semiconductor device having high withstand voltage is provided. An active groove 22a includes a long and narrow main groove part 26 and a sub groove part 27 connected to a longitudinal side surface of the main groove part, and a buried region 24 of a second conductivity type whose height is lower than the bottom surface of the base diffusion region 32a of the second conductivity type is provided on the bottom surface of the main groove part 26. An active groove filling region 25 of the second conductivity type in contact with the base diffusion region 32a is provided in the sub groove part 27. The buried region 24 is contacted to the base diffusion region 32a through the active groove filling region 25. Since one gate groove 83 is formed by the part above the buried region 24 in one active groove 22a, the gate electrode plugs 48 are not separated, which allows the electrode pattern to be simplified.
    Type: Application
    Filed: September 28, 2006
    Publication date: March 1, 2007
    Applicant: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Toru Kurosaki, Shinji Kunori, Mizue Kitada, Kosuke Ohshima, Hiroaki Shishido, Masato Mikawa
  • Patent number: 7135718
    Abstract: A semiconductor device having improved breakdown voltage is provided. A diode device of the present invention includes relay diffusion layers provided between guard ring portions. Therefore, a depletion layer expanded outward from the guard ring portions except the outermost one reaches these relay diffusion layers, and then the outer guard ring portions. The width of the distance between the guard ring portions is shorter where the relay diffusion layers are provided. For the width of the relay diffusion layers, the depletion layer reaches the outer guard ring portions with a lower voltage than the conventional structure.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: November 14, 2006
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Mizue Kitada, Kosuke Ohsima, Shinji Kunori, Toru Kurosaki
  • Publication number: 20060063335
    Abstract: A technique for improving a ruggedness of a transistor against breakdown is provided. In a transistor of the present invention, a height of filling regions is higher than that of buried regions, so that a withstanding voltage of the filling regions is higher than that of the buried regions. Therefore, since avalanche breakdown occurs in an active region, causing an avalanche breakdown current to flow through the active region having a large area, current concentration does not occur. As a result, a ruggedness of an element against breakdown is increased.
    Type: Application
    Filed: October 19, 2004
    Publication date: March 23, 2006
    Inventors: Toru Kurosaki, Hiroaki Shishido, Mizue Kitada, Shinji Kunori, Kosuke Ohshima
  • Publication number: 20050224848
    Abstract: An active groove filled region 23a is kept at a portion of an active groove 22a connecting to an embedded region 24 positioned below a gate groove 83. The active groove filled region 23a connects to a source electrode film 58a so as to have the same electric potential as a source region 64. When a reverse bias is applied between a base region 32a and a conductive layer 12, a reverse bias is also applied between the embedded region 24 and the conductive layer 12; and therefore, depletion layers spread out together and a withstanding voltage is increased.
    Type: Application
    Filed: April 4, 2005
    Publication date: October 13, 2005
    Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Toru Kurosaki, Shinji Kunori, Mizue Kitada, Kosuke Ohshima, Hiroaki Shishido
  • Patent number: 6906355
    Abstract: A semiconductor device having guard grooves uniformly filled with a semiconductor filler is provided. The four corners of a rectangular ring-shaped guard groove meet at right angles, and outer and inner auxiliary diffusion regions both rounded are connected to the four corners. Since the guard grooves do not have to be rounded, the plane orientation of a silicon single crystal exposed inside the guard grooves can be all {100}. Therefore, epitaxial growth in the guard grooves is uniformly carried out, and the grooves are filled with guard regions without defects.
    Type: Grant
    Filed: October 3, 2003
    Date of Patent: June 14, 2005
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Toru Kurosaki, Hiroaki Shishido, Mizue Kitada, Shinji Kunori, Kosuke Ohshima
  • Patent number: 6876034
    Abstract: A semiconductor device having grooves uniformly filled with semiconductor fillers is provided. Both ends of each of narrow active grooves are connected to an inner circumferential groove surrounding the active grooves. The growth speed of semiconductor fillers on both ends of the active grooves becomes equal to that at their central portions. As a result, a semiconductor device having the active grooves filled with the semiconductor fillers at a uniform height is obtained.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: April 5, 2005
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Toru Kurosaki, Hiroaki Shishido, Mizue Kitada, Shinji Kunori, Kosuke Ohshima
  • Patent number: 6841825
    Abstract: A technique for improving a ruggedness of a transistor against breakdown is provided. In a transistor of the present invention, a height of filling regions is higher than that of buried regions, so that a withstanding voltage of the filling regions is higher than that of the buried regions. Therefore, since avalanche breakdown occurs in an active region, causing an avalanche breakdown current to flow through the active region having a large area, current concentration does not occur. As a result, a ruggedness of an element against breakdown is increased.
    Type: Grant
    Filed: June 2, 2003
    Date of Patent: January 11, 2005
    Assignee: Shindengen Electric Manufacturing Co., Ltd.
    Inventors: Toru Kurosaki, Hiroaki Shishido, Mizue Kitada, Shinji Kunori, Kosuke Ohshima
  • Publication number: 20040070002
    Abstract: A semiconductor device having guard grooves uniformly filled with a semiconductor filler is provided. The four corners of a rectangular ring-shaped guard groove meet at right angles, and outer and inner auxiliary diffusion regions both rounded are connected to the four corners. Since the guard grooves do not have to be rounded, the plane orientation of a silicon single crystal exposed inside the guard grooves can be all {100}. Therefore, epitaxial growth in the guard grooves is uniformly carried out, and the grooves are filled with guard regions without defects.
    Type: Application
    Filed: October 3, 2003
    Publication date: April 15, 2004
    Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Toru Kurosaki, Hiroaki Shishido, Mizue Kitada, Shinji Kunori, Kosuke Ohshima
  • Publication number: 20040021195
    Abstract: A semiconductor device having grooves uniformly filled with semiconductor fillers is provided. Both ends of each of narrow active grooves are connected to an inner circumferential groove surrounding the active grooves. The growth speed of semiconductor fillers on both ends of the active grooves becomes equal to that at their central portions. As a result, a semiconductor device having the active grooves filled with the semiconductor fillers at a uniform height is obtained.
    Type: Application
    Filed: June 27, 2003
    Publication date: February 5, 2004
    Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Toru Kurosaki, Hiroaki Shishido, Mizue Kitada, Shinji Kunori, Kosuke Ohshima
  • Publication number: 20030227051
    Abstract: A technique for improving a ruggedness of a transistor against breakdown is provided. In a transistor of the present invention, a height of filling regions is higher than that of buried regions, so that a withstanding voltage of the filling regions is higher than that of the buried regions. Therefore, since avalanche breakdown occurs in an active region, causing an avalanche breakdown current to flow through the active region having a large area, current concentration does not occur. As a result, a ruggedness of an element against breakdown is increased.
    Type: Application
    Filed: June 2, 2003
    Publication date: December 11, 2003
    Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Toru Kurosaki, Hiroaki Shishido, Mizue Kitada, Shinji Kunori, Kosuke Ohshima
  • Publication number: 20030160262
    Abstract: A semiconductor device having improved breakdown voltage is provided. A diode device of the present invention includes relay diffusion layers provided between guard ring portions. Therefore, a depletion layer expanded outward from the guard ring portions except the outermost one reaches these relay diffusion layers, and then the outer guard ring portions. The width of the distance between the guard ring portions is shorter where the relay diffusion layers are provided. For the width of the relay diffusion layers, the depletion layer reaches the outer guard ring portions with a lower voltage than the conventional structure.
    Type: Application
    Filed: February 20, 2003
    Publication date: August 28, 2003
    Inventors: Mizue Kitada, Kosuke Ohsima, Shinji Kunori, Toru Kurosaki
  • Publication number: 20030042555
    Abstract: A transistor and diode having a low resistance and a high breakdown voltage are provided. When the bottom portion of a narrow trench having the shape of a rectangular parallelepiped is filled with a semiconductor grown by epitaxial method, a {1 0 0} plane is exposed at the sidewalls of the narrow trench. The semiconductor is epitaxially grown at a constant rate on each sidewall of the narrow trench; thereby, creating a filling material with no voids present therein. The concentration and width of the filling material are optimized. This allows the portion located between the filling materials in a drain layer to be completely depleted when the filling material is completely depleted; thereby, making it possible to establish an electric field having a constant strength in the depletion layer extended in the drain layer.
    Type: Application
    Filed: July 18, 2002
    Publication date: March 6, 2003
    Applicant: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Mizue Kitada, Kosuke Oshima, Toru Kurosaki, Shinji Kunori, Akihiko Sugai