Patents by Inventor Toru Maeda

Toru Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11574160
    Abstract: A non-contact communication medium according to one disclosed embodiment includes a memory unit, a power generation unit, a power monitoring unit, and a capacitance control unit. The power generation unit includes a resonant circuit and a rectification circuit, and generates electric power to be supplied to the memory unit. The resonant circuit includes an antenna coil and resonant capacitance unit having a variable capacitance value, and the rectification circuit rectifies a resonant output of the resonant circuit. The power monitoring unit includes a current adjustment element, a reference voltage generation source, and an operational amplifier. The operational amplifier controls the current adjustment element such that an output voltage of the rectification circuit is equal to a reference voltage from the reference voltage generation source. The capacitance control unit is configured to control the resonant capacitance unit on the basis of an output of the operational amplifier.
    Type: Grant
    Filed: March 19, 2019
    Date of Patent: February 7, 2023
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Kazutoshi Ono, Toru Terashima, Hiroaki Fujita, Hiroaki Nakano, Hideo Maeda, Nobuhiko Shigyo
  • Patent number: 11545462
    Abstract: A mounting apparatus for stacking and mounting two or more semiconductor chips at a plurality of locations on a substrate includes: a first mounting head for forming, at a plurality of locations on the substrate, temporarily stacked bodies in which two or more semiconductor chips are stacked in a temporarily press-attached state; and a second mounting head for forming chip stacked bodies by sequentially finally press-attaching the temporarily stacked bodies formed at the plurality of locations. The second mounting head includes: a press-attaching tool for heating and pressing an upper surface of a target temporarily stacked body to thereby finally press-attach the two or more semiconductor chips configuring the temporarily stacked body altogether; and one or more heat-dissipation tools having a heat-dissipating body which, by coming into contact with an upper surface of another stacked body positioned around the target temporarily stacked body, dissipates heat from the another stacked body.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: January 3, 2023
    Assignee: SHINKAWA LTD.
    Inventors: Tomonori Nakamura, Toru Maeda
  • Publication number: 20220372598
    Abstract: An aluminum alloy material comprising a composition containing no less than 1.2 at % and no more than 6.5 at % of Fe, no less than 0.15 at % and no more than 5 at % of at least one first element selected from the group consisting of Nd, W, and Sc, and no less than 0.005 at % and no more than 2 at % of at least one second element selected from the group consisting of C and B, the balance being Al and inevitable impurities.
    Type: Application
    Filed: March 22, 2021
    Publication date: November 24, 2022
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Toru MAEDA, Rui IWASAKI
  • Patent number: 11508689
    Abstract: A mounting apparatus for stacking and mounting two or more semiconductor chips at a plurality of locations on a substrate includes: a first mounting head for forming, at a plurality of locations on the substrate, temporarily stacked bodies in which two or more semiconductor chips are stacked in a temporarily press-attached state; and a second mounting head for forming chip stacked bodies by sequentially finally press-attaching the temporarily stacked bodies formed at the plurality of locations. The second mounting head includes: a press-attaching tool for heating and pressing an upper surface of a target temporarily stacked body to thereby finally press-attach the two or more semiconductor chips configuring the temporarily stacked body altogether; and one or more heat-dissipation tools having a heat-dissipating body which, by coming into contact with an upper surface of another stacked body positioned around the target temporarily stacked body, dissipates heat from the another stacked body.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: November 22, 2022
    Assignee: SHINKAWA LTD.
    Inventors: Tomonori Nakamura, Toru Maeda
  • Publication number: 20220357532
    Abstract: An embodiment optical circuit wafer includes a plurality of unit sections formed on a wafer. The plurality of unit sections are formed in each of first dies, second dies, and third dies. Further, each of the plurality of unit sections includes electrical pads formed in a common layout. Further, each of the plurality of unit sections includes optical input/output ports formed in a common layout. The input/output ports are, for example, grating couplers. Further, each of the plurality of unit sections includes optical circuits. The optical circuits have different circuit structures from one another.
    Type: Application
    Filed: June 17, 2019
    Publication date: November 10, 2022
    Inventors: Yoshiho Maeda, Toru Miura, Hiroshi Fukuda
  • Publication number: 20220349936
    Abstract: A stage, electric probes, an optical probe, an electric measurement device, an optical measurement device, and a first positioning mechanism are provided. The stage includes a second positioning mechanism that changes relative positional relationship between the electric probes and an electric connection portion of each of the optical elements. The electric probes electrically connect the electric measurement device and each of the optical elements. The optical probe optically connects the optical measurement device and each of the optical elements. The first positioning mechanism changes relative positional relationship between the optical probe and an optical connection portion of each of the optical elements.
    Type: Application
    Filed: June 17, 2019
    Publication date: November 3, 2022
    Inventors: Toru Miura, Yoshiho Maeda, Hiroshi Fukuda
  • Publication number: 20220347734
    Abstract: A structure includes: a first member made of metal having a tubular shape, and having a through-insertion hole; a second member made of resin and joined to the first member; and a third member made of metal having a tubular shape, and inserted through inside the first member. The third member is tube-expanded toward the first member and joined to the first member by press-fitting.
    Type: Application
    Filed: October 14, 2020
    Publication date: November 3, 2022
    Applicant: KABUSHIKI KAISHA KOBE SEIKO SHO (KOBE STEEL, LTD.)
    Inventors: Taiki YAMAKAWA, Toru HASHIMURA, Yasuhiro MAEDA
  • Publication number: 20220339689
    Abstract: A method joins members for joining a first member being cylindrical and a second member being plate-shaped and having an opening. This method includes: inserting a first member into an opening of the second member; inserting an elastic body into the first member; guiding an outer diameter side of the first member with a pair of outer dies on both sides of the second member; and compressing an elastic body in the first member with a pair of inner dies. The inner dies compress the elastic body within a range in which the outer dies are positioned.
    Type: Application
    Filed: September 14, 2020
    Publication date: October 27, 2022
    Applicant: Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.)
    Inventors: Yasuhiro MAEDA, Toru HASHIMURA, Taiki YAMAKAWA
  • Patent number: 11472359
    Abstract: A structural member for a vehicle includes bumper stays having a tubular configuration and fixed to each of front ends of a pair of front side members included in a vehicle, and a tubular bumper beam provided with holes and into which the bumper stay is inserted. Each of the bumper stays includes a first shock absorbing portion and a second shock absorbing portion provided adjacent to the first shock absorbing portion on an outer side.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: October 18, 2022
    Assignee: Kobe Steel, Ltd.
    Inventors: Taiki Yamakawa, Toru Hashimura, Yasuhiro Maeda
  • Patent number: 11442229
    Abstract: An optical waveguide in which a grating coupler is formed, a first pattern region arranged to surround the grating coupler, and a second pattern region arranged to surround the grating coupler are included. The first pattern region and the second pattern region are arranged adjacently. In a periphery of the grating coupler, the first pattern region is formed in a region continuous in a circumferential direction. Similarly, in the periphery of the grating coupler, the second pattern region is formed in a region continuous in the circumferential direction.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: September 13, 2022
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Toru Miura, Yoshiho Maeda, Hiroshi Fukuda
  • Patent number: 11433450
    Abstract: A joined body includes: a first member having a pipe shape; and a second member including a wall portion having a plate shape, and a flange portion having a cylinder shape provided with an insertion hole through which the first member is inserted. In a state where the first member is inserted into the insertion hole of the flange portion of the second member, the first member and the second member are joined with the first member pipe-expanded. A material of the second member is larger than a material of the first member in a spring-back amount.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: September 6, 2022
    Assignee: Kobe Steel, Ltd.
    Inventors: Yasuhiro Maeda, Kenichi Watanabe, Takayuki Kimura, Toru Hashimura
  • Publication number: 20220275896
    Abstract: A joined body includes a tubular first member, and a second member including a plate-shaped wall portion in which a through-hole is formed, the first member being inserted into the through-hole. The collar member is interposed between the first member and the second member in at least a part of the hole peripheral wall of the through-hole. The first member and the second member are joined by expanding the first member at a portion corresponding to the through-hole.
    Type: Application
    Filed: July 16, 2020
    Publication date: September 1, 2022
    Applicant: KABUSHIKI KAISHA KOBE SEIKO SHO (KOBE STEEL, LTD.)
    Inventors: Yasuhiro MAEDA, Toru HASHIMURA, Taiki YAMAKAWA
  • Patent number: 11415752
    Abstract: An optical inspection circuit includes an optical circuit to be inspected formed on a substrate, an input optical waveguide optically connected to the optical circuit, and an output optical waveguide optically connected to the optical circuit. The input optical waveguide is connected with a grating coupler for input. The grating coupler is connected with the input optical waveguide via a spot size conversion unit. The output optical waveguide is optically connected with a photodiode.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: August 16, 2022
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Hiroshi Fukuda, Toru Miura, Yoshiho Maeda
  • Publication number: 20220229317
    Abstract: In an embodiment, an optical inspection circuit includes: an optical modulator comprising an optical waveguide on a substrate, the optical waveguide having a core comprising a semiconductor; a first input waveguide optically connected to the optical modulator, the first input waveguide having a core comprising the semiconductor; an output waveguide optically connected to the optical modulator, the output waveguide having a core comprising the semiconductor; a photodiode on the substrate in a vicinity of the optical modulator; a wire electrically connecting the optical modulator and the photodiode; and a second input waveguide optically connected to the photodiode, the second input waveguide having a core comprising the semiconductor.
    Type: Application
    Filed: May 23, 2019
    Publication date: July 21, 2022
    Inventors: Hiroshi Fukuda, Toru Miura, Yoshiho Maeda
  • Patent number: 11378740
    Abstract: An optical waveguide is provided and includes: a core forming layer with a high refractive index; and a first clad layer with a low refractive index, bonded to a first main surface of the core forming layer. The core forming layer is provided in its plane direction with a core portion, lateral clad portions each having one side adjacent to a corresponding side of the core portion, and high refractive index portions each adjacent to the other side of a corresponding one of the lateral clad portions. The core portion is provided in its plane direction with a central region, and GI regions in each of which a refractive index continuously decreases from the central region toward an interface with the corresponding one of the lateral clad portions. The lateral clad portions each include a region having a constant refractive index.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: July 5, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shingo Maeda, Naoyuki Kondou, Toru Nakashiba, Junko Kurizoe
  • Publication number: 20220195562
    Abstract: An aluminum alloy having a composition including 0.1% by mass or more and 2.8% by mass or less of Fe; and 0.002% by mass or more and 2% by mass or less of Nd.
    Type: Application
    Filed: April 2, 2020
    Publication date: June 23, 2022
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Rui IWASAKI, Toru MAEDA, Tetsuya KUWABARA
  • Publication number: 20220136088
    Abstract: An aluminum alloy material including 1.2 atom % or more and 6.5 atom % or less of Fe, and 0.005 atom % or more and less than 0.15 atom % of one or more elements selected from the group consisting of Nd, W, and Sc, with the balance being Al and unavoidable impurities.
    Type: Application
    Filed: December 20, 2019
    Publication date: May 5, 2022
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Toru MAEDA, Rui IWASAKI
  • Patent number: 11296048
    Abstract: Provided is a mounting device in which two or more semiconductor chips are laminated and mounted at a plurality of locations on a substrate, said mounting device including: a stage that supports the substrate; a bonding part that laminates and mounts the plurality of semiconductor chips on the substrate while heating the plurality of semiconductor chips and the substrate; and a heat insulating member that is interposed between the stage and the substrate, said heat insulating member including a first layer which is in contact with the substrate and to which heat is applied from the bonding part via the semiconductor chips and the substrate, and a second layer which is disposed closer to the stage side than the first layer, wherein the first layer has a larger heat resistance than the second layer.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: April 5, 2022
    Assignee: SHINKAWA LTD.
    Inventors: Tomonori Nakamura, Toru Maeda
  • Patent number: 11201132
    Abstract: Provided is a method for setting the conditions for heating a semiconductor chip during bonding of the semiconductor chip using an NCF, wherein a heating start temperature and a rate of temperature increase are set on the basis of a viscosity characteristic map that indicates changes in viscosity with respect to temperature of the NCF at various rates of temperature increase and a heating start temperature characteristic map that indicates changes in viscosity with respect to temperature of the NCF when the heating start temperature is changed at the same rate of temperature increase.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: December 14, 2021
    Assignee: SHINKAWA LTD.
    Inventors: Tomonori Nakamura, Toru Maeda, Satoru Nagai, Yoshihiro Saeki, Osamu Watanabe
  • Patent number: 11172600
    Abstract: A semiconductor mounting device for mounting chip components on a substrate, wherein the device is reduced in size. A semiconductor mounting device 10 comprises: a temporary placement stage 12 on which are loaded a plurality of chip components 30a, 30b, 30c; a conveyance head 14 that conveys the chip components 30a, 30b, 30c to the temporary placement stage 12, and also loads each of the chip components 30a, 30b, 30c on the temporary placement stage 12 so that the relative positions of the plurality of chip components 30a, 30b, 30c reach predetermined positions; a mounting stage 16 that secures a substrate 36 by suction; and a mounting head 18 that suctions the plurality of chip components 30a, 30b, 30c loaded on the temporary placement stage 12, and pressurizes while keeping the relative positions at prescribed positions on the substrate 36 that is secured by suction to the mounting stage 16.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: November 9, 2021
    Assignee: SHINKAWA LTD.
    Inventors: Tomonori Nakamura, Toru Maeda