Patents by Inventor Toru Meura
Toru Meura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11174402Abstract: The thermosetting resin composition for LDS of the invention includes a thermosetting resin, an inorganic filler, a non-conductive metal compound that forms a metal nucleus upon irradiation with active energy rays, and a coupling agent, in which the non-conductive metal compound includes one or more selected from the group consisting of a spinel-type metal oxide, a metal oxide having two or more transition metal elements in groups adjacent to each other, the groups being selected from groups 3 to 12 of the periodic table, and a tin-containing oxide, and the coupling agent includes one or more selected from the group consisting of mercaptosilane, aminosilane, and epoxysilane.Type: GrantFiled: April 10, 2017Date of Patent: November 16, 2021Assignee: SUMITOMO BAKELITE CO., LTD.Inventor: Toru Meura
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Publication number: 20190292386Abstract: The thermosetting resin composition for LDS of the invention includes a thermosetting resin, an inorganic filler, a non-conductive metal compound that forms a metal nucleus upon irradiation with active energy rays, and a coupling agent, in which the non-conductive metal compound includes one or more selected from the group consisting of a spinel-type metal oxide, a metal oxide having two or more transition metal elements in groups adjacent to each other, the groups being selected from groups 3 to 12 of the periodic table, and a tin-containing oxide, and the coupling agent includes one or more selected from the group consisting of mercaptosilane, aminosilane, and epoxysilane.Type: ApplicationFiled: April 10, 2017Publication date: September 26, 2019Applicant: SUMITOMO BAKELITE CO., LTD.Inventor: Toru MEURA
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Patent number: 9349714Abstract: A method of manufacturing a semiconductor device is provided which is capable of improving productivity and reliability. The method of manufacturing a semiconductor device (1) of the invention includes a sequential stacking process, an individual stacked body-obtaining process, and a base material bonding process. In the sequential stacking process, a block stacked body is obtained. The block stacked body is a block stacked body (2B) in which semiconductor blocks (10B, 12B, 14B, and 16B) are stacked in a state of not being solder-bonded. In the semiconductor blocks (10B, 12B, 14B, and 16B), a plurality of semiconductor components are arranged. In the individual stacked body obtaining process, an individual stacked body (2) is obtained in which terminals of the stacked semiconductor components are solder-bonded and which is cut from the block stacked body (2B) in a stacked semiconductor component unit.Type: GrantFiled: August 24, 2012Date of Patent: May 24, 2016Assignee: SUMITOMO BAKELITE CO., LTD.Inventors: Kensuke Nakamura, Toru Meura, Yoji Ishimura
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Patent number: 9123830Abstract: Provided is a method of manufacturing a semiconductor device that has a plurality of semiconductor components and a plurality of resin layers, the method including: a step in which resin layers and semiconductor components are laminated alternately on a substrate, and the same is adhered by being subjected to heating and pressurization at a temperature lower than the temperature at which the substrate and/or a solder layer of the semiconductor components melts; and a step in which heat and pressure are applied at a temperature at which the solder layer melts or a temperature higher than said temperature.Type: GrantFiled: November 12, 2012Date of Patent: September 1, 2015Assignee: SUMITOMO BAKELITE CO., LTD.Inventors: Kensuke Nakamura, Toru Meura, Yoji Ishimura
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Publication number: 20140312511Abstract: Provided is a method of manufacturing a semiconductor device that has a plurality of semiconductor components and a plurality of resin layers, the method including: a step in which resin layers and semiconductor components are laminated alternately on a substrate, and the same is adhered by being subjected to heating and pressurization at a temperature lower than the temperature at which the substrate and/or a solder layer of the semiconductor components melts; and a step in which heat and pressure are applied at a temperature at which the solder layer melts or a temperature higher than said temperature.Type: ApplicationFiled: November 12, 2012Publication date: October 23, 2014Inventors: Kensuke Nakamura, Toru Meura, Yoji Ishimura
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Publication number: 20140183758Abstract: A method of manufacturing a semiconductor device is provided which is capable of improving productivity and reliability. The method of manufacturing a semiconductor device (1) of the invention includes a sequential stacking process, an individual stacked body-obtaining process, and a base material bonding process. In the sequential stacking process, a block stacked body is obtained. The block stacked body is a block stacked body (2B) in which semiconductor blocks (10B, 12B, 14B, and 16B) are stacked in a state of not being solder-bonded. In the semiconductor blocks (10B, 12B, 14B, and 16B), a plurality of semiconductor components are arranged. In the individual stacked body obtaining process, an individual stacked body (2) is obtained in which terminals of the stacked semiconductor components are solder-bonded and which is cut from the block stacked body (2B) in a stacked semiconductor component unit.Type: ApplicationFiled: August 24, 2012Publication date: July 3, 2014Applicant: SUMITOMO BAKELITE CO., LTD.Inventors: Kensuke Nakamura, Toru Meura, Yoji Ishimura
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Publication number: 20130324641Abstract: Provided is a method for manufacturing an electronic component by using a solder joining method for bonding a first electronic component having a metal electrode with a second electronic component having a solder electrode, the method comprising; (i) forming a resin layer containing a thermosetting resin on at least one of the solder joint surfaces of said first electronic component and said second electronic component; (ii) positioning said metal electrode of said first electronic component and said solder electrode of said second electronic component to face each other, heating said positioned electrodes and applying pressure, and thereby bringing said metal electrode and said solder electrode into contact; (iii) heating electronic components while applying pressure thereby fusion bonding said solder to said metal electrode; and (iv) heating said resin layer.Type: ApplicationFiled: August 8, 2013Publication date: December 5, 2013Applicant: Sumitomo Bakelite Co., Ltd.Inventors: Kenzou MAEJIMA, Satoru KATSURAYAMA, Toru MEURA
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Patent number: 8598719Abstract: A semiconductor element mounting board includes: a board having surfaces; a semiconductor element provided at a side of one of the surfaces of the board; a bonding agent layer through which the board and the semiconductor element are bonded together, the bonding agent layer having a storage modulus at 25° C. of 5 to 1,000 MPa; a first layer into which the semiconductor element is embedded, the first layer provided on the one surface of the board; a second layer provided on the other surface of the board, the second layer being constituted from the same material as that of the first layer, the constituent material of the second layer having the same composition ratio as that of the constituent material of the first layer; and surface layers provided on the first and second layers, respectively, each of the surface layers being formed from at least a single layer.Type: GrantFiled: June 3, 2009Date of Patent: December 3, 2013Assignee: Sumitomo Bakelite Company LimitedInventors: Mitsuo Sugino, Hideki Hara, Toru Meura
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Patent number: 8531028Abstract: Provided is a method for manufacturing an electronic component by using a solder joining method for bonding a first electronic component having a metal electrode with a second electronic component having a solder electrode, the method comprising; (i) forming a resin layer containing a thermosetting resin on at least one of the solder joint surfaces of said first electronic component and said second electronic component; (ii) positioning said metal electrode of said first electronic component and said solder electrode of said second electronic component to face each other, heating said positioned electrodes and applying pressure, and thereby bringing said metal electrode and said solder electrode into contact; (iii) heating electronic components while applying pressure thereby fusion bonding said solder to said metal electrode; and (iv) heating said resin layer.Type: GrantFiled: July 9, 2010Date of Patent: September 10, 2013Assignee: Sumitomo Bakelite Co., Ltd.Inventors: Kenzou Maejima, Satoru Katsurayama, Toru Meura
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Patent number: 8389328Abstract: Provided is a method of manufacturing an electronic device having a first electronic component having a first terminal and a second electronic component having a second terminal, wherein the first electric component is electrically connected to the second electronic component by connecting the first terminal to the second terminal with solder, the method including: providing a resin layer having a flux action between the first terminal and the second terminal to obtain a laminate including the first electronic component, the second electronic component, and the resin layer, wherein a solder is provided on the first terminal or the second terminal; soldering the first terminal and the second terminal; and curing the resin layer while pressing the laminate with a pressurized fluid.Type: GrantFiled: October 30, 2009Date of Patent: March 5, 2013Assignee: Sumitomo Bakelite Co., Ltd.Inventors: Toru Meura, Kenzou Maejima, Yoji Ishimura, Mina Nikaido
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Patent number: 8269332Abstract: A semiconductor element mounting board includes: aboard having surfaces; a semiconductor element mounted on one of the surfaces of the board; a first layer into which the semiconductor element is embedded, the first layer being provided on the one surface of the board; a second layer provided on the other surface of the board, the second layer being constituted from the same material as that of the first layer, the constituent material of the second layer having the same composition ratio as that of the constituent material of the first layer; and surface layers provided on the first and second layers, respectively, each of the surface layers being formed from at least a single layer. In such a semiconductor element mounting board, each of the surface layers has rigidity higher than that of each of the first and second layers. It is preferred that in the case where a Young's modulus of each surface layer at 25° C. is defined as X GPa and a Young's modulus of the first layer at 25° C.Type: GrantFiled: October 15, 2008Date of Patent: September 18, 2012Assignee: Sumitomo Bakelite Company, Ltd.Inventors: Mitsuo Sugino, Hideki Hara, Toru Meura
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Publication number: 20120199988Abstract: Disclosed is a method of manufacturing an electronic device, that includes obtaining a stack of the first electronic component and the second electronic component, while placing a resin layer which contains a flux-active compound and a thermosetting resin, between the first terminals and the second terminals; bonding the first terminals and the second terminals with solder, by heating the stack at a temperature not lower than the melting point of solder layers on the first terminals, while pressurizing the stack using a fluid; and curing the resin layer. The duration from the point of time immediately after the start of heating of the stack, up to the point of time when the temperature of the stack reaches the melting point of the solder layers, is set to 5 seconds or longer, and 15 minutes or shorter.Type: ApplicationFiled: October 13, 2010Publication date: August 9, 2012Applicant: Sumitomo Bakelite Co., Ltd.Inventors: Toru Meura, Hiroki Nikaido, Kenzou Maejima, Yoji Ishimura, Kenji Yoshida
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Patent number: 8227703Abstract: A multilayered circuit board of the present invention has a single-side laminated structure and does not include a core substrate having via-holes formed therethrough and vias for providing electrical connection through the via-holes. The multilayered circuit board includes a plurality of pairs of layers, each pair including a conductor circuit layer and an insulator layer, wherein a glass transition temperature of each insulator layer is 170° C. or higher, a coefficient of thermal expansion at the glass transition temperature or lower of each insulator layer is 35 ppm or less, and a modulus of elasticity of each insulator layer is 5 GPa or more.Type: GrantFiled: January 17, 2008Date of Patent: July 24, 2012Assignee: Sumitomo Bakelite Company, Ltd.Inventors: Hironori Maruyama, Kensuke Nakamura, Toru Meura, Hiroshi Hirose
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Publication number: 20120118939Abstract: The process for manufacturing the semiconductor device and the apparatus, which achieve stable production of semiconductor devices with improved connection reliability, is presented. First terminals of circuit boards 1 are arranged to face the corresponding bumps of semiconductor chips 2, respectively, and the resin layer 3 is disposed between the respective first terminals and the respective bumps to form laminates, and the laminates are simultaneously compressed from a direction of lamination, while heating a plurality of laminates. In such case, the diaphragm 54 disposed in a heating furnace 51 is abutted against a plurality of laminates or a member 531 to elastically deform the members while a plurality of laminates is heated in the heating furnace 51, so that laminates are simultaneously compressed from a direction of lamination, while heating thereof in a vacuum.Type: ApplicationFiled: November 14, 2011Publication date: May 17, 2012Applicants: SUMITOMO BAKELITE CO., LTD., ELPIDA MEMORY, INC.Inventors: Keiyo KUSANAGI, Koichi HATAKEYAMA, Mitsuhisa WATANABE, Yusuke NAKANOYA, Hidenori MATSUSHITA, Toru MEURA, Kenzou MAEJIMA, Hiroki NIKAIDO, Mina NIKAIDO
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Publication number: 20120061820Abstract: Provided is a method for manufacturing an electronic component by using a solder joining method for bonding a first electronic component having a metal electrode with a second electronic component having a solder electrode, the method comprising; (i) forming a resin layer containing a thermosetting resin on at least one of the solder joint surfaces of said first electronic component and said second electronic component; (ii) positioning said metal electrode of said first electronic component and said solder electrode of said second electronic component to face each other, heating said positioned electrodes and applying pressure, and thereby bringing said metal electrode and said solder electrode into contact; (iii) heating electronic components while applying pressure thereby fusion bonding said solder to said metal electrode; and (iv) heating said resin layer.Type: ApplicationFiled: July 9, 2010Publication date: March 15, 2012Inventors: Kenzou Maejima, Satoru Katsurayama, Toru Meura
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Patent number: 8079141Abstract: The method for providing the solder connection of the present invention is a method for providing a solder connection, which electrically connects a first electronic component having a solder bump to a second electronic component having a protruded electrode to provide electrical connection between the first solder bump and the protruded electrode, wherein a relation of: A+B>C is satisfied, where a height of the first solder bump from one surface of the first electronic component is presented as A [?m], a height of the protruded electrode before the compressive deformation from one surface of the second electronic component is presented as B [?m], and a thickness of the adhesive agent layer is presented as C [?m], and further comprising: disposing the adhesive agent layer in the first electronic component; and deforming the first solder bump and the protruded electrode and providing a contact of the above-described protruded electrode with the above-described first solder bump, so that the sum of the heighType: GrantFiled: February 24, 2009Date of Patent: December 20, 2011Assignee: Sumitomo Bakelite Co., Ltd.Inventor: Toru Meura
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Publication number: 20110221075Abstract: Provided is a method of manufacturing an electronic device comprising a first electronic component having a first terminal and a second electronic component having a second terminal, wherein said first electric component is electrically connected to said second electronic component by connecting said first terminal to said second terminal with solder, the method comprising, providing a resin layer having a flux action between said first terminal and said second terminal to obtain a laminate including said first electronic component, said second electronic component, and said resin layer, wherein a solder is provided on said first terminal or said second terminal; soldering said first terminal and said second terminal; and curing said resin layer while pressing said laminate with a pressurized fluid.Type: ApplicationFiled: October 30, 2009Publication date: September 15, 2011Applicant: SUMITOMO BAKELITE CO., LTD.Inventors: Toru Meura, Hiroki Nikaido, Mina Nikaido, Kenzou Maejima, Yoji Ishimura
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Publication number: 20110084409Abstract: A semiconductor element mounting board includes: a board having surfaces; a semiconductor element provided at a side of one of the surfaces of the board; a bonding agent layer through which the board and the semiconductor element are bonded together, the bonding agent layer having a storage modulus at 25° C. of 5 to 1,000 MPa; a first layer into which the semiconductor element is embedded, the first layer provided on the one surface of the board; a second layer provided on the other surface of the board, the second layer being constituted from the same material as that of the first layer, the constituent material of the second layer having the same composition ratio as that of the constituent material of the first layer; and surface layers provided on the first and second layers, respectively, each of the surface layers being formed from at least a single layer.Type: ApplicationFiled: June 3, 2009Publication date: April 14, 2011Inventors: Mitsuo Sugino, Hideki Hara, Toru Meura
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Publication number: 20100313416Abstract: The method for providing the solder connection of the present invention is a method for providing a solder connection, which electrically connects a first electronic component having a solder bump to a second electronic component having a protruded electrode to provide electrical connection between the first solder bump and the protruded electrode, wherein a relation of: A+B>C is satisfied, where a height of the first solder bump from one surface of the first electronic component is presented as A [?m], a height of the protruded electrode before the compressive deformation from one surface of the second electronic component is presented as B [?m], and a thickness of the adhesive agent layer is presented as C [?m], and further comprising: disposing the adhesive agent layer in the first electronic component; and deforming the first solder bump and the protruded electrode and providing a contact of the above-described protruded electrode with the above-described first solder bump, so that the sum of the heighType: ApplicationFiled: February 24, 2009Publication date: December 16, 2010Applicant: Sumitomo Bakelite Co., LtdInventor: Toru Meura
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Publication number: 20100213597Abstract: A semiconductor element mounting board includes: aboard having surfaces; a semiconductor element mounted on one of the surfaces of the board; a first layer into which the semiconductor element is embedded, the first layer being provided on the one surface of the board; a second layer provided on the other surface of the board, the second layer being constituted from the same material as that of the first layer, the constituent material of the second layer having the same composition ratio as that of the constituent material of the first layer; and surface layers provided on the first and second layers, respectively, each of the surface layers being formed from at least a single layer. In such a semiconductor element mounting board, each of the surface layers has rigidity higher than that of each of the first and second layers. It is preferred that in the case where a Young's modulus of each surface layer at 25° C. is defined as X GPa and a Young's modulus of the first layer at 25° C.Type: ApplicationFiled: October 15, 2008Publication date: August 26, 2010Applicant: SUMITOMO BAKELITE COMPANY LIMITEDInventors: Mitsuo Sugino, Hideki Hara, Toru Meura